W49V002 Winbond, W49V002 Datasheet - Page 22

• Manufacturer Part Number: W49V002
• Description: 256K X 8 CMOS FLASH MEMORY WITH FWH INTERFACE
• Manufacturer: Winbond

TIMING WAVEFORMS FOR LPC INTERFACE MODE
Read Cycle Timing Diagram
Write Cycle Timing Diagram
LAD[3:0]
#RESET
#LFRAM
LAD[3:0]
#RESET
#LFRAM
CLK
CLK
1 Clock
1 Clock
T
SU
0000b
Start
0000b
Start
T
HD
1 Clock
1 Clock
Memory
Read
Cycle
010Xb
Memory
Write
Cycle
011Xb
Load Address in 8 Clocks, the address should be within the top 4MByte,
FFFFFFFF to FFC00000, or within the bottom 1MByte, 000FFFFF to 000E0000.
A[31:28] A[27:24]
Load Address in 8 Clocks, the address should be within the top 4MByte,
FFFFFFFF to FFC00000, or within the bottom 1MByte, 000FFFFF to 000E0000.
A[31:28] A[27:24]
A[23:20] A[19:16]
A[23:20] A[19:16]
T
T CYC
CYC
Address
Address
A[15:12]
A[15:12]
- 22 -
T
A[11:8]
A[11:8]
SU
T
HD
A[7:4]
A[7:4]
A[3:0]
A[3:0]
Preliminary W49V002A
Load Data in 2 Clocks
1111b
D[3:0]
2 Clocks
Data
TAR
T
Tri-State 0000b
D[7:4]
SU
T
HD
1 Clock
1111b
Sync
2 Clocks
T
KQ
TAR
Tri-State
Data out 2 Clocks
D[3:0]
Data
1 Clock
0000b
D[7:4]
Sync
TAR
TAR
Next Start
1 Clock
1 Clock
Next Start
0000b
0000b