MACH5 Lattice, MACH5 Datasheet - Page 26

• Manufacturer Part Number: MACH5
• Description: Fifth Generation MACH Architecture
• Manufacturer: Lattice

CAPACITANCE
1. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where
I
These curves represent the typical power consumption for a particular device at system frequency.
The selected “typical” pattern is a 16-bit up-down counter. This pattern fills the device and
exercises every macrocell. Maximum frequency shown uses internal feedback and a D-type
register. Power/Speed are optimized to obtain the highest counter frequency and the lowest
power. The highest frequency (LSBs) is placed in common PAL blocks, which are set to high
power. The lowest frequency signals (MSBs) are placed in a common PAL block and set to
lowest power. For a more detailed discussion about MACH 5 power consumption, refer to the
application note entitled MACH 5 Power in the Application Notes section on the Lattice Data Book
CD-ROM or Lattice web site.
I
26
C
C
CC
CC
IN
I/O
Parameter Symbol
these parameters may be affected.
vs. FREQUENCY
700
600
500
400
300
200
100
CURVES AT HIGH /LOW POWER MODES
0
1
Description
Parameter
I/CLK pin
I/O pin
Figure 8. I
V
CC
V
M5-128/1 and M5LV-128 low power
V
M5(LV)-512 low power
M5(LV)-384 low power
M5(LV)-320 low power
OUT
CC
IN
Curves at High/Low Power Modes
=2.0 V
= 5 V or 3.3 V, T
=2.0 V
MACH 5 Family
Frequency (MHz)
M5-256/1 and M5LV-256 low power
M5-192/1 low power
Test conditions
3.3 V or 5 V, 25º C, 1 MHz
3.3 V or 5 V, 25º C, 1 MHz
A
= 25º C
M5-128/1 and M5LV-128 high power
Typ
12
10
M5(LV)-512 high power
M5(LV)-384 high power
M5(LV)-320 high power
M5-192/1 high power
M5-256/1 and
M5LV-25 high power
20446G-048
Unit
pF
pF