K7A801800 Samsung semiconductor, K7A801800 Datasheet - Page 16

• Manufacturer Part Number: K7A801800
• Description: 256Kx36 & 512Kx18-Bit Synchronous Pipelined Burst SRAM
• Manufacturer: Samsung semiconductor

K7A403600B
K7A403200B
K7A401800B
APPLICATION INFORMATION
DEPTH EXPANSION
The Samsung 128Kx36 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 128K depth to 256K depth without extra logic.
INTERLEAVE READ TIMING
64-Bits
Microprocessor
(ADSP CONTROLLED , ADSC=HIGH)
Clock
ADSP
ADDRESS
[0:n]
WRITE
CS
A
ADV
OE
Data Out
(Bank 0)
Data Out
(Bank 1)
n+1
1
Address
t
SS
Data
*Notes : n = 14 32K depth
ADS
CLK
A1
t
SH
t
WS
15 64K depth
16 128K depth
17 256K depth
t
LZOE
Bank 0 is selected by CS
A
[0:17]
t
ADVS
t
t
WH
OE
CLK
Q1-1
(Refer to non-interleave write timing for interleave write timing)
Cache
Controller
Address
t
ADVH
128Kx36/x32 & 256Kx18 Synchronous SRAM
2
, and Bank 1 deselected by CS
Q1-2
A
Q1-3
- 16 -
[17]
t
CSS
t
AS
A
Q1-4
CS
CS
CLK
ADSC
WEx
OE
CS
[0:16]
A2
2
Address
t
2
2
1
HZC
ADV
t
t
AH
CSH
t
LZC
t
CD
128Kx36
SPB
SRAM
(Bank 0)
ADSP
Bank 0 is deselected by CS
Data
Q2-1
I/O
[0:71]
A
[17]
Q2-2
2
, and Bank 1 selected by CS
A
Don t Care
CS
CS
CLK
ADSC
WEx
OE
CS
[0:16]
Address
2
2
1
ADV
Q2-3
128Kx36
SPB
SRAM
(Bank 1)
ADSP
Data
Nov 2001
Undefined
Rev 1.0
Q2-4
2