AS7C34098-10 ALSC [Alliance Semiconductor Corporation], AS7C34098-10 Datasheet - Page 2

• Manufacturer Part Number: AS7C34098-10
• Description: 5V/3.3V 256K x 16 CMOS SRAM
• Manufacturer: ALSC [Alliance Semiconductor Corporation]

Functional description
The AS7C4098 and AS7C34098 are high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) devices
organized as 262,144 words × 16 bits. They are designed for memory applications where fast data access, low power, and
simple interfacing are desired.
Equal address access and cycle times (t
ideal for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank
memory systems.
When CE is High the device enters standby mode. The standard AS7C4098/AS7C34098 is guaranteed not to exceed 110/
72mW power consumption in CMOS standby mode. A write cycle is accomplished by asserting write enable (WE) and chip
enable (CE). Data on the input pins I/O1–I/O16 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To
avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or
write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) High. The chip
drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or
All chip inputs and outputs are TTL- and CMOS-compatible, and operation is from either a single 5V (AS7C4098) or 3.3V
(AS7C34098) supply. Both devices are available in the JEDEC standard 400-mL, 44-pin SOJ and TSOP 2 packages.
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
write enable is active, output drivers stay in high-impedance mode.
These devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to
be written and read. LB controls the lower bits, I/O1–I/O8, and UB controls the higher bits, I/O9–I/O16.
Absolute maximum ratings
Truth table
Voltage on V
Voltage on any pin relative to GND
Power dissipation
Storage temperature
Ambient temperature with V
DC current into outputs (low)
Key: X = Don’t care, L = Low, H = High.
1/13/05; v.1.9
CE
H
L
L
L
L
CC
Parameter
WE
relative to GND
X
H
X
H
L
CC
OE
X
H
X
X
L
applied
AA
, t
LB
X
X
H
H
H
L
L
L
L
RC
AS7C34098
AS7C4098
Alliance Semiconductor
, t
Device
WC
) of 10/12/15/20 ns with output enable access times (t
UB
X
X
H
H
H
L
L
L
L
Symbol
T
I
T
V
V
V
OUT
P
bias
stg
D
t1
t1
t2
I/O1–I/O8
®
High Z
High Z
High Z
High Z
D
D
D
D
OUT
OUT
IN
IN
–0.50
–0.50
–0.50
Min
–65
–55
–
–
I/O9–I/O16
High Z
High Z
High Z
High Z
D
D
D
D
OUT
OUT
IN
IN
V
CC
+150
+125
Max
+7.0
+5.0
±20
1.5
+0.50
Output disable (I
Standby (I
OE
Write (I
Read (I
) of 5/6/7/8 ns are
AS7C34098
Mode
AS7C4098
P. 2 of 10
SB
CC
CC
, I
Unit
)
mA
)
°C
°C
SB1
W
V
V
V
CC
)
)