ADIS16136/PCBZ AD [Analog Devices], ADIS16136/PCBZ Datasheet - Page 16

• Manufacturer Part Number: ADIS16136/PCBZ
• Manufacturer: AD [Analog Devices]

Table 31. MSC_CTRL Bit Descriptions
Bits
[15:12]
11
10
9
8
7
[6:3]
2
1
0
Table 32. GPIO_CTRL Bit Descriptions
Bits
[15:12]
11
10
9
8
[7:4]
3
2
1
0
SELF TEST
The MSC_CTRL bits (see Table 31) provide a self test function
that helps verify the mechanical integrity of the MEMS and
signal processing circuit. When enabled, the self test applies an
electrostatic force to the internal sensor element, which causes it
to move in a manner that simulates its response to actual rotation.
There are two self test options in the MSC_CTRL register: auto-
matic and manual. Set MSC_CTRL[10] = 1 (DIN = 0x9D04) to
run the automatic self test routine, which reports a pass/fail result
ADIS16136
Description (Default = 0x0006)
Not used
Memory test (cleared upon completion)
(1 = enabled, 0 = disabled)
Automatic self test (cleared upon completion)
(1 = enabled, 0 = disabled)
Manual self test
(1 = enabled, 0 = disabled)
Not used
Disable sensor compensation
(1 = disable compensation, 0 = enable compensation)
Not used
Data ready enable
(1 = enabled, 0 = disabled)
Data ready polarity
(1 = active high, 0 = active low)
Data ready line select
(1 = DIO2, 0 = DIO1)
Description (Default = 0x0000)
Don’t care
General-Purpose I/O Line 4 (DIO4) data level
General-Purpose I/O Line 3 (DIO3) data level
General-Purpose I/O Line 2 (DIO2) data level
General-Purpose I/O Line 1 (DIO1) data level
Don’t care
General-Purpose I/O Line 2 (DIO2) direction control
(1 = output, 0 = input)
General-Purpose I/O Line 1 (DIO1) direction control
(1 = output, 0 = input)
General-Purpose I/O Line 2 (DIO2) direction control
(1 = output, 0 = input)
General-Purpose I/O Line 1 (DIO1) direction control
(1 = output, 0 = input)
Rev. A | Page 16 of 20
in DIAG_STAT[5]. MSC_CTRL[10] resets itself to 0 after com-
pleting this routine. This process takes approximately 45 ms. Set
MSC_CTRL[9] = 1 (DIN = 9D02) to manually activate the self test
function, and set MSC_CTRL[9] = 0 (DIN = 9D00) to manually
deactivate the self test function. Measure the output bias for each
condition, calculate the difference between them, and compare
it to the expected self test response shown in Table 1.
POWER MANAGEMENT
The SLP_CTRL register (see Table 33) provides two different
sleep modes for system level management: normal and timed.
Set SLP_CTRL[7:0] = 0xFF (DIN = 0xA4FF) to start normal
sleep mode. To awaken the device from sleep mode, use one of
the following options to restore normal operation: assert CS from
high to low, pulse RST low, then high again, or cycle the power. Use
SLP_CTRL[7:0] to put the device into sleep mode for a specified
period. For example, SLP_CTRL[7:0] = 0x64 (DIN = 0xA464)
puts the
Table 33. SLP_CTRL Bit Descriptions
Bits
[15:8]
[7:0]
STATUS
The DIAG_STAT register (see Table 34) provides error flags for
a number of functions. Each flag uses a 1 to indicate an error
condition and a 0 to indicate a normal condition. Reading this
register provides access to the status of each flag and resets all of
the bits to 0 for monitoring future operation. If the error
condition remains, the error flag returns to 1 at the conclusion
of the next sample cycle. The SPI communication error flag in
DIAG_STAT[3] indicates that the number of SCLKs in a SPI
sequence did not equal a multiple of 16 SCLKs.
Table 34. DIAG_STAT Bit Descriptions
Bits
[15:10]
9
8
7
6
5
4
3
2
[1:0]
ADIS16136
Description
Not used
0xFF: normal sleep mode
0x00 to 0xFE: programmable sleep time bits; 0.5 sec/LSB
Description (Default = 0x0000)
Not used
Alarm 2 status (1 = active, 0 = inactive)
Alarm 1 status (1 = active, 0 = inactive)
Not used
Flash test, checksum flag (1 = fail, 0 = pass)
Self test diagnostic error flag (1 = fail, 0 = pass)
Sensor over range (1 = over range, 0 = normal)
SPI communication failure (1 = fail, 0 = pass)
Flash update failure (1 = fail, 0 = pass)
Not used
to sleep for 50 sec.
Data Sheet