ADIS16201/PCB AD [Analog Devices], ADIS16201/PCB Datasheet - Page 24

• Manufacturer Part Number: ADIS16201/PCB
• Description: Programmable Dual-Axis
• Manufacturer: AD [Analog Devices]

ADIS16201
SMPL_PRD Register Definition
Address
0x37, 0x36
1
The data within this register is nonvolatile, allowing for data
recovery upon reset. The initial value is set to 0x04 upon initial
power-up, allowing for a sample period of 610 μs.
Table 24. SMPL_PRD Bit Descriptions
Bit
15:8
7
6:0
FILTERING CONTROL
The ADIS16201 has the ability to perform basic filtering on the
seven output data variables through the AVG_CNT control
register. The filtering performed is that of a low-pass, moving
average filter. The size of the data being averaged (number of
filter taps) is determined through the AVG_CNT control
register. The filtering applied through the AVG_CNT control
register is applied to all seven data output variables concurrently
and, thus, one output variable cannot be filtered differently
from another.
The number of taps (N) within the moving average filter is
calculated as
where AVG_CNT is shown as a decimal value. With AVG_CNT
set to 00h, N is reduced to 1, which effectively disables the
moving average filter.
At the other extreme, when AVG_CNT is set to its maximum
setting of 08h, N increases to 256, effectively reducing the
apparent bandwidth by 256. Note that the contribution from
each tap is set to 1/(N) allowing for unity gain in the filter
response. The frequency response of the moving average filter is
given as:
Default is valid only until the first register write cycle.
N
H
(
=
f
2
)
Description
Not used.
ADC time base control. The MSB and TMBS set the
time base of the acquisition system to 122.1 μs when
SR7 = 0 vs. 3.784 ms when SR7 = 1.
ADC Sample Period Count. The lower 7 bits, SP6 to
SP0, represent a binary count that, when added to
one and then multiplied by the time base, results in
the combined sample period of the ADC. (Combined
sample period being the period required to sample
and update all seven data outputs.) Minimum setting
for the lower 7 bits, SP6 to SP0, is 0x01. The overall
acquisition time can be varied from 244.2 μs to
15.51 ms in 122.1 μs increments for TMBS = 0 and
from 7.57 ms to 481 ms in 3.784 ms increments for
TMBS = 1. This equates to the sample rate varying
from 4096 SPS to 64.5 SPS for TMBS = 0 and from
132 SPS to 2.08 SPS for TMBS = 1.
AVG
=
sin(
N
_
CNT
sin(
Default
0x0004
π
×
π
N
×
×
f
1
f
×
×
t
t
s
s
)
)
Format
N/A
Access
R/W
Rev. A | Page 24 of 32
The more taps, the more poles, thus the steeper the slope of the
roll-off. Use caution with this filter mechanism because the
amplitudes of the sideband peaks within the stop band are not
reduced with an increasing number of taps, potentially allowing
for high frequency components to leak through. Sample
frequency response plots for the moving average filter, utilizing
various numbers of taps, are detailed in Figure 37.
AVG_CNT Register Definition
Address
0x39, 0x38
1
The AVG_CNT register contains information that represents
the number of averages to be applied to the output data. The
number of averages can be calculated by powers of 2. For
example, the default value of the register, 4, would result in 16
averages applied to the output data. The number of averages can
be set to 1, 2, 4, 8, 16, 32, 64, 128, and 256.
Table 25. AVG_CNT Bit Description
Bit
15:4
3:0
POWER-DOWN CONTROL
The ADIS16201 has the ability to power down for user-defined
amounts of time, using the PWR_MDE control register. The
amount of time specified by the PWR_MDE control register is
equal to the binary count of the 8-bit control word multiplied by
0.5 seconds. Therefore, the 255 codes cover an overall shutdown
time period of 127.5 seconds. The PWR_MDE register is volatile
and is set to 0 upon both initial power-up and subsequent wake-
ups from the power-down period. By setting the PWR_MDE
control register to a non-zero state, the ADIS16201 automatically
powers down once the next sample period is completed and the
seven data output registers are updated.
Default is valid only until the first register write cycle.
–0.5
H(f)
1.0
0.5
0
Figure 37. Number of Taps vs. Sample Frequency Response
0
Description
Not used
Data bits (maximum = 1000, or a decimal value of 8)
N = 16
Default
0x0004
0.1
N = 4
1
FREQUENCY (Hz)
0.2
Format
Binary
0.3
N = 2
0.4
Access
R/W
0
.5
f/fs