EVAL-AD1934EB AD [Analog Devices], EVAL-AD1934EB Datasheet - Page 20

• Manufacturer Part Number: EVAL-AD1934EB
• Description: 8-Channel DAC with PLL, 192 kHz, 24 Bits
• Manufacturer: AD [Analog Devices]

AD1934
CONTROL REGISTERS
DEFINITIONS
The format is the same for I
I
volume registers that are set to full volume.
Note that the first setting in each control register parameter is the default setting.
Table 14. Register Format
Bit
Table 15. Register Addresses and Functions
Address
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PLL AND CLOCK CONTROL REGISTERS
Table 16. PLL and Clock Control 0
Bit
0
2:1
4:3
6:5
7
2
C, ADR0 and ADR1 are OR’ e d into Bit 17 and Bit 8 to provide multiple chip addressing. All registers are reset to 0, except for the DAC
Global Address
23:17
Value
0
1
00
01
10
11
00
01
10
11
00
01
10
11
0
1
Function
Normal operation
Power-down
INPUT 256 (×44.1 kHz or 48 kHz)
INPUT 384 (×44.1 kHz or 48 kHz)
INPUT 512 (×44.1 kHz or 48 kHz)
INPUT 768 (×44.1 kHz or 48 kHz)
XTAL oscillator enabled
256 × f
512 × f
Off
MCLK
DLRCLK
AUXTDMLRCLK
Reserved
Disable: DAC idle
Enable: DAC active
2
C and SPI ports. The global address for the AD1934 is 0x04, shifted left 1 bit due to the R/ W bit. However, in
S
S
VCO output
VCO output
Function
PLL and Clock Control 0
PLL and Clock Control 1
DAC Control 0
DAC Control 1
DAC Control 2
DAC individual channel mutes
DAC 1L volume control
DAC 1R volume control
DAC 2L volume control
DAC 2R volume control
DAC 3L volume control
DAC 3R volume control
DAC 4L volume control
DAC 4R volume control
Reserved
Auxiliary TDM Port Control 0
Auxiliary TDM Port Control 1
R/W
16
Rev. 0 | Page 20 of 28
Description
PLL power-down
MCLK pin functionality (PLL active)
MCLKO pin
PLL input
Internal MCLK enable
Register Address
15:8
Data
7:0