EVAL-AD7321CB AD [Analog Devices], EVAL-AD7321CB Datasheet - Page 29

• Manufacturer Part Number: EVAL-AD7321CB
• Description: 500 kSPS, 2-Channel, Software-Selectable, True Bipolar Input, 12-Bit Plus Sign ADC
• Manufacturer: AD [Analog Devices]

AUTO SHUTDOWN MODE
(PM1 = 1, PM0 = 0)
Once the autoshutdown mode is selected, the AD7321 auto-
matically enters shutdown on the 15
autoshutdown mode, all internal circuitry is powered down.
The AD7321 retains information in the registers during
autoshutdown. The track-and-hold is in hold mode during
autoshutdown. On the rising
which was in hold during shutdown, returns to track as the
AD7321 begins to power up. The power-up from autoshutdown
is 500 μs.
When the control register is programmed to transition to
autoshutdown mode, it does so on the 15
Figure 47 shows the part entering autoshutdown mode. The
AD7321 automatically begins to power up on the CS rising
edge. The t
by bringing the CS signal low, can take place. Once this valid
conversion is complete, the AD7321 powers down again on the
15
keep the part in autoshutdown mode.
AUTOSTANDBY MODE
(PM1 = 0, PM0 =1)
In autostandby mode, portions of the AD7321 are powered
down, but the on-chip reference remains powered up. The
reference bit in the control register should be 1 to ensure that
the on-chip reference is enabled. This mode is similar to auto-
shutdown but allows the AD7321 to power up much faster,
which allows faster throughput rates.
th
SDATA
SCLK
SCLK rising edge. The CS signal must remain low again to
DIN
CS
POWER-UP
CONTROL REGISTER IS LOADED ON THE FIRST 15 CLOCKS,
1
is required before a valid conversion, initiated
DATA INTO CONTROL REGISTER
CS edge, the track-and-hold,
PART ENTERS SHUTDOWN MODE
ON THE 15TH RISING SCLK EDGE
AS PM1 = 1, PM0 = 0
PM1 = 1, PM0 = 0
VALID DATA
th
SCLK rising edge. In
th
SCLK rising edge.
Figure 47. Entering Autoshutdown/Autostandby Mode
15
PART BEGINS TO POWER
UP ON CS RISING EDGE
16
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As is the case with autoshutdown mode, the AD7321 enters
standby on the 15
is updated (see
registers during standby. The AD7321 remains in standby until
it receives a
CS
was in hold mode while the part was in standby, returns to track.
The power-up time from standby is 700 ns. The user should
ensure that 700 ns have elapsed before bringing CS low to
attempt a valid conversion. Once this valid conversion is
complete, the AD7321 again returns to standby on the 15
SCLK rising edge. The CS signal must remain low to keep the
part in standby mode.
Figure 47 shows the part entering autoshutdown mode. The
sequence of events is the same when entering autostandby
mode. In Figure 47, the power management bits are configured
for autoshutdown. For autostandby mode, the power
management bits, PM1 and PM0, should be set to 0 and 1,
respectively.
t
POWER-UP
rising edge. On the
THE PART IS FULLY POWERED UP
ONCE
CS rising edge. The ADC begins to power up on the
t
POWER-UP
1
Figure 47). The part retains information in the
th
SCLK rising edge once the control register
HAS ELAPSED
DATA INTO CONTROL REGISTER
CS
rising edge, the track-and-hold, which
VALID DATA
15
AD7321
16
th