EVAL-AD73422EB AD [Analog Devices], EVAL-AD73422EB Datasheet - Page 16

• Manufacturer Part Number: EVAL-AD73422EB
• Description: Dual Low Power CMOS Analog Front End with DSP Microcomputer
• Manufacturer: AD [Analog Devices]

AD73422
Control
Bit 15
Bit 14
Bits 13–11 Device Address
Bits 10–8
Bits 7–0
C D
5 1
/
C
C
O
O
N
N
/ R W
4 1
Frame
Control/Data
Read/Write
Register Address This 3-bit field is used to select one of the five control registers on the AFE section of the AD73422.
Register Data
T
T
R
R
O
O
L
L
D
3 1
R
R
E
E
E
V
G
G
I
C
I
I
E
S
S
2 1
T
T
A
E
E
D
Description
When set high, it signifies a control word in Program or Mixed Program/Data Modes. When set low, it
signifies a data word in Mixed Program/Data Mode or an invalid control word in Program Mode.
When set low, it tells the device that the data field is to be written to the register selected by the regis-
ter field setting provided the address field is zero. When set high, it tells the device that the selected
register is to be written to the data field in the input serial register and that the new control word is to
be output from the device via the serial output.
This 3-bit field holds the address information. Only when this field is zero is a device selected. If the
address is not zero, it is decremented and the control word is passed out of the device via the serial
output.
This 8-bit field holds the data that is to be written to or read from the selected register provided the
address field is zero.
R
R
D
R
A
B
E
1 1
S
S
Bit
0
1
2
3
4
5
6
7
Bit
0
1
2
3
4
5
6
7
R
R
0 1
Table XII. Control Register B Description
E
Table XI. Control Register A Description
C
E
G
S
E
7
7
Table X. Control Word Description
I
S
E
E
Name
DATA/PGM
MM
DLB
SLB
DC0
DC1
DC2
RESET
Name
DIR0
DIR1
SCD0
SCD1
MCD0
MCD1
MCD2
CEE
T
T
E
R
9
M
A
D
D
C
6
6
C
D
D
2
R
2
E
8
S
–16–
S
M
Description
Operating Mode (0 = Program; 1 = Data Mode)
Mixed Mode (0 = Off; 1 = Enabled)
Digital Loop-Back Mode (0 = Off; 1 = Enabled)
SPORT Loop-Back Mode (0 = Off; 1 = Enabled)
Device Count (Bit 0)
Device Count (Bit 1)
Device Count (Bit 2)
Software Reset (0 = Off; 1 = Initiates Reset)
Description
Decimation/Interpolation Rate (Bit 0)
Decimation/Interpolation Rate (Bit 1)
Serial Clock Divider (Bit 0)
Serial Clock Divider (Bit 1)
Master Clock Divider (Bit 0)
Master Clock Divider (Bit 1)
Master Clock Divider (Bit 2)
Control Echo Enable (0 = Off; 1 = Enabled)
D
C
5
C
5
D
1
7
1
M
D
C
4
6
4
C
D
0
0
S
5
S
C
L
3
3
D
R
B
E
1
G
4
I
S
T
S
D
E
C
L
2
2
R
D
B
D
0
3
A
T
A
D
M
I
1
1
2
M
R
1
D
P
G
A
D
1
M
T
I
0
0
R
A
0
/
REV. 0
0