EVAL-AD7662CB AD [Analog Devices], EVAL-AD7662CB Datasheet - Page 4

• Manufacturer Part Number: EVAL-AD7662CB
• Description: Evaluation Board AD766X/AD767X
• Manufacturer: AD [Analog Devices]

Designation with the control
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
JP13
JP14
JP15
JP16
JP17
JP18
JP19
JP20
EVAL-AD766XCB/AD767XCB
Test Point
Jumper
Table III. EVAL-AD766XCB/AD767XCB Test Points
Default position
board ( Factory
settings)
VANA1 ADC analog supply
D G N D Digital ground
D G N D Digital ground
S I G +
AGND Analog ground close to SIG+
R E F
BUSY
AGND Analog ground close to REF
F
O V D D ADC digital output supply
DVDD ADC digital core supply
AGND Analog ground close to SIG-
SIG-
A, U3 side
A, U3 side
A, U3 side
A, U3 side
A, U3 side
A, U3 side
not A
not A
SYNC
Available Signal
ADC Analog input
ADC Reference input
ADC BUSY signal
ADC
ADC
ADC
MCLK divided by 2
ADC Analog input
PRELIMINARY TECHNICAL DATA
signal
signal
Selection of IMPULSE. When the button of the switch is close to J4 connector
( not A position ), the ADC uses the IMPULSE mode which is the mode with the
lowest power dissipation. With the AD7660, JP13 is a spare switch.
TEST1. For factory use only and it is pull down.
TEST0. For factory use only and it is pull down.
Selection of EXT/
the switch is close to J4 connector ( not A position ) and when the serial reading
mode is selected, the data are read with an external serial clock SCLK generated from
the master clock MCLK otherwise the data are read with the ADC serial clock. When
external serial clock reading mode is selected, MCLK has to be fast enough to be able
the read the data properly as explained in the AD766X data sheet. JP16 has no use in
parallel reading mode.
Selection of INVSYNC ( SYNC active level ). When the button of the switch is close
to J4 connector ( not A position ) and when the master serial reading mode is se
lected, the SYNC signal is active Low. JP17 has no use in parallel reading mode or
slave serial reading mode.
Selection of INVSCLK ( SCLK active edge ). When the button of the switch is close
to J4 connector ( not A position ) and when the serial reading mode is selected,
INVSCLK is high. JP18 has no use in parallel reading mode.
Selection of
otherwise the on-board
the on-board
Selection of REF signal. When JP20 is in position A, the REF is buffered. When
JP20 is not in position A, the REF is not buffered.
signal
TABLE II. JUMPER DESCRIPTION
signal. When JP19 is in position A, the signal on J3 is used
Function
– 4 –
signal.
( use of external or internal serial clock ). When the button of
Table IV. Component values Vs. Input ranges ( AD7660 )
0 to -5V
Table V. Component values Vs. Input ranges ( AD7664 )
0 to -5V
Input range
± 10V
± 5V
Input range
± 10V
± 5V
generation is used. MCLK signal is used to generate
R1
8k
8k
8k
R1
2k
2k
1k
1k
250
R3
R3
2k
8k
500
1k
8k
6.67k
0
8k
6.67k
0
R6
R6
R7
R7
10k
10k
none
10k
10k
none
REV. PrK