HY27US08121B HYNIX [Hynix Semiconductor], HY27US08121B Datasheet - Page 15

• Manufacturer Part Number: HY27US08121B
• Description: 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
• Manufacturer: HYNIX [Hynix Semiconductor]

SERIAL PRESENCE DETECT
Rev. 0.2/Dec. 02
Byte#
36~40 Reserved for VCSDRAM
46~61 Superset information(may be used in future)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
41
42
43
44
45
62
63
0
1
2
3
4
5
6
7
8
9
Number of Bytes written into serial memory at module
manufacturer
Total number of Bytes in SPD device
Fundamental memory type
Number of row address on this assembly
Number of column address on this assembly
Number of physical banks on DIMM
Module data width
Module data width (continued)
Module voltage Interface levels(VDDQ)
DDR SDRAM cycle time at CAS Latency=2.5(tCK)
DDR SDRAM access time from clock at CL=2.5 (tAC)
Module configuration type
Refresh rate and type
Primary DDR SDRAM width
Error checking DDR SDRAM data width
Minimum clock delay for back-to-back random column
address(tCCD)
Burst lengths supported
Number of banks on each DDR SDRAM
CAS latency supported
CS latency
WE latency
DDR SDRAM module attributes
DDR SDRAM device attributes : General
DDR SDRAM cycle time at CL=2.0(tCK)
DDR SDRAM access time from clock at CL=2.0(tAC)
DDR SDRAM cycle time at CL=1.5(tCK)
DDR SDRAM access time from clock at CL=1.5(tAC)
Minimum row precharge time(tRP)
Minimum row activate to row active delay(tRRD)
Minimum RAS to CAS delay(tRCD)
Minimum active to precharge time(tRAS)
Module row density
Command and address signal input setup time(tIS)
Command and address signal input hold time(tIH)
Data signal input setup time(tDS)
Data signal input hold time(tDH)
Minimum active / auto-refresh time ( tRC)
Minimum auto-refresh to active/auto-refresh
command period(tRFC)
Maximum cycle time (tCK max)
Maximim DQS-DQ skew time(tDQSQ)
Maximum read data hold skew factor(tQHS)
SPD Revision code
Checksum for Bytes 0~62
Function Description
0.75ns
7.5ns
7.5ns
0.9ns
0.9ns
0.5ns
0.5ns
0.5ns
15ns
15ns
15ns
45ns
60ns
75ns
12ns
M
Concurrent Auto Precharge
+/-0.2Voltage tolerance,
Differential Clock Input
Function Supported
7.8us & Self refresh
+/-0.75ns
+/-0.75ns
0.75ns
7.5ns
7.5ns
0.9ns
0.9ns
0.5ns
0.5ns
0.5ns
tRAS Lock Out
20ns
15ns
20ns
45ns
65ns
75ns
12ns
DDR SDRAM
Initial release
K
SSTL 2.5V
Undefined
Undefined
128 Bytes
256 Bytes
Non-ECC
4 Banks
256MB
64 Bits
1Bank
1 CLK
2, 2.5
2,4,8
N/A
13
10
x8
0
1
-
-
-
-
0.75ns
HYMD232646B(L)8-M/K/H/L
7.5ns
0.9ns
0.9ns
0.5ns
0.5ns
0.5ns
10ns
20ns
15ns
20ns
45ns
65ns
75ns
12ns
H
Bin Sort :M(DDR266(2-2-2),K(DDR266A@CL=2)
+/-0.8ns
+/-0.8ns
0.75ns
8.0ns
1.1ns
0.6ns
0.6ns
0.6ns
1.1ns
10ns
20ns
15ns
20ns
50ns
70ns
80ns
12ns
L
H(DDR266B@CL=2.5),L(DDR200@CL=2)
3Ch
3Ch
3Ch
2Dh
3Ch
4Bh
8Ah
75h
75h
75h
75h
90h
90h
50h
50h
30h
32h
75h
M
3Ch
2Dh
4Bh
75h
75h
75h
75h
50h
50h
90h
90h
50h
50h
41h
30h
32h
75h
B7h
Hexa Value
K
0Dh
0Ch
C0h
80h
08h
07h
0Ah
01h
40h
00h
04h
00h
08h
00h
01h
0Eh
04h
01h
02h
20h
00h
00h
40h
00h
00h
00h
82h
3Ch
2Dh
A0h
50h
4Bh
E2h
75h
75h
75h
50h
90h
90h
50h
50h
41h
30h
32h
75h
H
A0h
3Ch
B0h
B0h
3Ch
7Ch
80h
80h
80h
50h
50h
32h
60h
60h
46h
50h
30h
75h
L
Note
1
1
2
2
2
2
2
2
15