EVAL-AD9388AFEZ_1 AD [Analog Devices], EVAL-AD9388AFEZ_1 Datasheet - Page 19

• Manufacturer Part Number: EVAL-AD9388AFEZ_1
• Description: 10-Bit Integrated, Multiformat, HDTV Video Decoder, RGB Graphics Digitizer, and 2:1 Multiplexed HDMI/DVI Interface
• Manufacturer: AD [Analog Devices]

Processor
CP
CP
CP
CP
CP
CP
CP
CP
CP
CP
CP
CP
CP
Processor
CP
CP
CP
1
2
3
4
Table 9. Component Processor Pixel Output Pin Map (P29 to P20)
CP processor uses digitizer or HDMI as input.
Maximum pixel clock rate of 54 MHz.
Maximum pixel clock rate of 170 MHz for the analog digitizer.
Maximum pixel clock rate of 165 MHz for HDMI.
1
1
Mode/Format
Mode 1
Video output
8-bit 4:2:2
Mode 2
Video output
10-bit 4:2:2
Mode 3
Video output
12-bit 4:2:2
Mode 4
Video output
12-bit 4:2:2
Mode 5
Video output
12-bit 4:2:2
Mode 6
Video output
16-bit 4:2:2
Mode 7
Video output
20-bit 4:2:2
Mode 8
Video output
20-bit 4:2:2
Mode 9
Video output
24-bit 4:2:2
Mode 10
Video output
24-bit 4:2:2
Mode 11
Video output
24-bit 4:2:2
Mode 12
Video output
24-bit 4:4:4
Mode 13
Video output
24-bit 4:4:4
Mode/Format
Mode 17
Video output
30-bit 4:4:4
Mode 18
Video output
30-bit 4:4:4
Mode 19
Video output
30-bit 4:2:2
2
3, 4
3, 4
2
2
3, 4
2
2
3, 4
3, 4
3, 4
3, 4
3, 4
29
–
–
–
–
–
–
–
–
Y[1:0]
19
28
–
–
–
–
–
–
–
–
CHC[9:0] (default data is B[9:0] or Cb[9:0])
CHC[9:0] (default data is B[9:0] or Cb[9:0])
CHA[9:0] (default data is G[9:0] or Y[9:0])
18
CrCb[3:0]
17
27
–
–
–
–
–
–
–
CHC[7:0] (for example, B[7:0] or Cb[7:0])
CHB[7:0] (for example, R[7:0] or Cr[7:0])
CrCb[1:0]
CrCb[1:0]
16
Rev. B | Page 19 of 28
15
26
–
–
–
–
–
–
–
14
Output of Data Port Pins P[29:20]
C
rCb[11:4]
Output of Data Port Pins P[19:0]
13
25
–
–
–
–
–
–
–
–
12 11 10
24
–
–
–
–
–
–
–
–
YCrCb[3:0]
Y[3:0]
9
CHC[9:0] (default data is B[9:0] or Cb[9:0])
CHB[9:0] (default data is R[9:0] or Cr[9:0])
CHA[9:0] (default data is G[9:0] or Y[9:0])
8
23
–
–
–
–
–
–
YCrCb[1:0]
7
Y[1:0]
6
22
–
–
–
–
–
–
5
4
21
–
–
–
–
–
–
–
–
–
–
–
–
–
AD9388A
3
2
20
1 0
–
–
–
–
–
–
–
–
–
–
–
–
–