EVAL-ADE7816EBZ AD [Analog Devices], EVAL-ADE7816EBZ Datasheet - Page 43

• Manufacturer Part Number: EVAL-ADE7816EBZ
• Description: Six Current Channels, One Voltage Channel
• Manufacturer: AD [Analog Devices]

Data Sheet
Table 26. ACCMODE Register (Address 0xE701)
Bits
7
6
[5:4]
[3:2]
[1:0]
Table 27. LCYCMODE Register (Address 0xE702)
Bits
7
6
[5:4]
3
2
1
0
Table 28. HSDC_CFG Register (Address 0xE706)
Bits
[7:6]
5
[4:3]
2
1
0
Table 29. CONFIG2 Register (Address 0xEC01)
Bits
[7:2]
1
0
Bit Name
REVRPSEL
REVAPSEL
Reserved
VARACC[1:0]
WATTACC[1:0]
Bit Name
Reserved
RSTREAD
Reserved
ZX_SEL
Reserved
LVAR
LWATT
Bit Name
Reserved
HSAPOL
HXFER[1:0]
HGAP
HSIZE
HCLK
Bit Name
Reserved
I2C_LOCK
EXTREFEN
Default
Value
0x0
0x0
0x00
0x00
0x00
Default
Value
0x0
0x1
0x0
0x0
0x0
0x0
0x0
0x00
0x00
Default
Value
0x0
0x0
0x0
Default
Value
0x0
0x0
0x0
0x0
0: the sign of the reactive power is monitored on the A, B, and C channels.
0: the sign of the active power is monitored on the A, B, and C channels.
These bits should be ignored and not modified.
00: signed accumulation for all active power measurements.
These bits should be ignored.
Enables the voltage channel zero-crossing counter for line cycle accumulation mode.
Enables the reactive energy line cycle accumulation mode.
Enables the active energy line cycle accumulation mode.
These bits should be ignored.
00 = reserved.
These bits should be ignored.
Description
1: the sign of the reactive power is monitored on the D, E, and F channels.
1: the sign of the active power is monitored on the D, E, and F channels.
00: signed accumulation for all reactive power measurements.
01: reserved.
10: reserved.
11: reserved.
01: reserved.
10: reserved.
11: reserved.
Description
Reserved. This bit does not control any functionality.
Enables read-with-reset for all energy registers. Note that this bit has no function in line cycle
accumulation mode and should be set to 0 when this mode is in use.
These bits should be ignored.
Description
0: SS/HSA output pin is active low (default).
1: SS/HSA output pin is active high.
01 = HSDC transmits current and voltage waveform data.
10 = reserved.
11 = reserved.
0: no gap is introduced between packages (default).
1: a gap of seven HCLK cycles is introduced between packages.
0: HSDC transmits the 32-bit registers in 32-bit packages, most significant bit first (default).
1: HSDC transmits the 32-bit registers in 8-bit packages, most significant bit first.
0: HSCLK = 8 MHz (default).
1: HSCLK = 4 MHz.
Description
Serial port lock.
Set to 1 to use with an external reference.
Rev. 0| Page 43 of 48
ADE7816