EVAL-ADV7320EB AD [Analog Devices], EVAL-ADV7320EB Datasheet - Page 8

• Manufacturer Part Number: EVAL-ADV7320EB
• Description: Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs
• Manufacturer: AD [Analog Devices]

ADV7320/ADV7321
TIMING SPECIFICATIONS
V
specifications T
Table 4.
Parameter
MPU PORT
ANALOG OUTPUTS
CLOCK CONTROL AND PIXEL PORT
PIPELINE DELAY
1
2
3
4
Guaranteed by characterization.
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition.
Data: C[9:0]; Y[9:0], S[9:0]
Control: P_HSYNC , P_VSYNC , P_BLANK , S_HSYNC , S_VSYNC , S_BLANK
SD, PS = 27 MHz, HD = 74.25 MHz.
AA
SCLOCK Frequency
SCLOCK High Pulse Width, t
SCLOCK Low Pulse Width, t
Hold Time (Start Condition), t
Setup Time (Start Condition), t
Data Setup Time, t
SDATA, SCLOCK Rise Time, t
SDATA, SCLOCK Fall Time, t
Setup Time (Stop Condition), t
RESET Low Time
Analog Output Delay
Output Skew
f
f
Clock High Time, t
Clock Low Time, t
Data Setup Time, t
Data Hold Time, t
SD Output Access Time, t
SD Output Hold Time, t
HD Output Access Time, t
HD Output Hold Time, t
CLK
CLK
= 2.375 V to 2.625 V, V
1
MIN
4
to T
12
10
9
5
11
1
1
MAX
2
14
14
(0°C to 70°C), unless otherwise noted.
13
DD
13
2
7
1
6
= 2.375 V to 2.625 V, V
3
8
4
3
Min
0
0.6
1.3
0.6
0.6
100
0.6
100
40
40
2.0
2.0
5.0
5.0
Typ
7
1
81
63
76
35
41
36
DD_IO
Max
400
300
300
29.5
15
14
= 2.375 V to 3.6 V, V
Unit
kHz
µs
µs
µs
µs
ns
ns
ns
µs
ns
ns
ns
MHz
MHz
% of one clk cycle
% of one clk cycle
ns
ns
ns
ns
ns
ns
clk cycles
clk cycles
clk cycles
clk cycles
clk cycles
Rev. 0 | Page 8 of 88
REF
= 1.235 V, R
Test Conditions
First clock generated after this period relevant for
repeated start condition
SD PAL square pixel mode
PS/HD async mode
SD (2×, 16×)
SD component mode (16×)
PS (1×)
PS (8×)
HD (2×, 1×)
SET
= 3040 Ω, R
LOAD
= 300 Ω. All