LB11826_08 SANYO [Sanyo Semicon Device], LB11826_08 Datasheet - Page 9

• Manufacturer Part Number: LB11826_08
• Description: For OA Products Three-Phase Brushless Motor Driver
• Manufacturer: SANYO [Sanyo Semicon Device]

Continued from preceding page.
LB11826 Description
1. Speed control circuit
2. Output drive circuit
3. Current limiting circuit
4. Power save circuit
5. Reference clock
Pin No.
This IC performs speed control by using both the speed discriminator circuit and PLL circuit. The speed control circuit
outputs the error signal once for every two cycles of FG (one FG cycle counted). The PLL circuit outputs the phase
error signal once for each cycle of FG.
As the FG servo frequency is calculated as follows, the motor speed is set with the number of FG pulses and clock
frequency.
This IC achieves variable speed control with ease when combined with LB11825M.
This IC employs a direct PWM drive method to minimize the power loss at output. The output Tr is always saturated at
ON, and the motor drive force is adjusted through change of the duty at which the output is turned ON. Since the output
PWM switching is made with the lower-side output Tr, it is necessary to connect the schottky diode between OUT and
V CC (because the through current flows at an instant when the lower-side Tr is turned ON if the diode with a short
reverse recovery time is not used). The diode between OUT and GND is incorporated. When the large output current
presents problem (waveform disturbance at kickback on the lower side), connect a commutating diode or schottky
diode externally.
The current limiting circuit performs limiting with the current determined from I = V RF /Rf (V RF = 0.5Vtyp, Rf :
current detector resistance) (that is, this circuit limits the peak current).
Limiting operation includes decrease in the output on-duty to suppress the current.
This IC enters the power save condition to decrease the current dissipation in the stop mode. In this condition, the bias
current of most of circuits is cut off. Even in the power save condition, the 5 V regulator output is given.
This is entered from the external signal source (1MHz max) via a resistor (reference : about 5.1kΩ) in series with the XI
pin. The XO pin is left open.
22
21
24
23
26
25
27
Pin name
f FG (servo) = f CLK /512
f CLK : Clock frequency
Input signal source levels :
IN1 +
IN2 +
IN3 +
Low-level voltage : 0 to 0.8V
High-level voltage : 2.5 to 5.0V
IN1 -
IN2 -
IN3 -
F/R
Hall amplifier input.
IN + > IN - is the input high state, and the reverse is
the input low state.
It is recommended that the Hall signal has an
amplitude of 100mVp-p (differential) or more.
Connect a capacitor between the IN + and IN - inputs
if there is noise in the Hall sensor signals.
Forward/reverse control pin.
Low : 0V to 1.5V
High : 3.5V to VREG
H level when open.
Hysteresis width about 0.5V.
Pin function
LB11826
21 23 25
VREG
300Ω
VREG
Equivalent circuit
300Ω
22kΩ
2kΩ
22 24 26
No.7109-9/11
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