DM54L72J NSC [National Semiconductor], DM54L72J Datasheet

DM54L72J

Manufacturer Part Number

DM54L72J

Description

AND-Gated Master-Slave J-K Flip-Flop with Preset, Clear and Complementary Outputs

Manufacturer

NSC [National Semiconductor]

Datasheet

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C 1995 National Semiconductor Corporation

DM54L72 AND-Gated Master-Slave J-K Flip-Flop

with Preset Clear and Complementary Outputs

General Description

This device contains a positive pulse triggered master-slave

J-K flip-flop with complementary outputs Multiple J and K

inputs are ANDed together to produce the internal J and K

function for the flip-flop The J and K data is processed by

the flip-flop after a complete clock pulse While the clock is

low the slave is isolated from the master On the positive

transition of the clock the data from the AND gates is trans-

ferred to the master While the clock is high the AND gate

Connection Diagram

Order Number DM54L72J or DM54L72W

See NS Package Number J14A or W14B

Dual-In-Line Package

TL F 6629

TL F 6629 – 1

inputs are disabled On the negative transition of the clock

the data from the master is transferred to the slave The

logic state of the J and K inputs must not be allowed to

change while the clock is in the high state Data is trans-

ferred to the outputs on the falling edge of the clock pulse

A low logic level on the preset or clear inputs sets or resets

the outputs regardless of the logic levels of the other inputs

Function Table

Note 1 J

clock is high Data is transferred to the outputs on the falling edge of the

clock pulse

tablished

and or clear inputs return to their inactive (high) level

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each complete high level clock pulse

This configuration is nonstable that is it will not persist when the preset

Low Logic Level

Either Low or High Logic Level

High Logic Level

The output logic level before the indicated input conditions were es-

Positive pulse The J and K inputs must be held constant while the

CLR

Each output changes to the complement of its previous level on

(J1)(J2)(J3) K

CLK

Inputs

(Note 1)

(K1)(K2)(K3)

(Note 1)

RRD-B30M105 Printed in U S A

Outputs

June 1989

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DM54L72J Summary of contents

Page 1

... AND gates is trans- ferred to the master While the clock is high the AND gate Connection Diagram Dual-In-Line Package Order Number DM54L72J or DM54L72W See NS Package Number J14A or W14B C 1995 National Semiconductor Corporation TL F 6629 inputs are disabled On the negative transition of the clock ...

Page 2

Absolute Maximum Ratings If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage Input Voltage Operating Free Air Temperature Range DM54L Storage Temperature Range 65 ...

Page 3

Electrical Characteristics over recommended operating free air temperature (unless otherwise noted) Symbol Parameter V High Level Output Voltage Low Level Output Voltage Input Current Max ...

Page 4

... Fran ais Tel ( Italiano National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications Order Number DM54L72J NS Package Number J14A Order Number DM54L72W ...

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