ADSP2181KST-160 Analog Devices, ADSP2181KST-160 Datasheet

ADSP2181KST-160

Manufacturer Part Number

ADSP2181KST-160

Description

Manufacturer

Analog Devices

Datasheet

1.ADSP2181KST-160.pdf (32 pages)

Specifications of ADSP2181KST-160

Case

QFP

Date_code

08+

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ICE-Port is a trademark of Analog Devices, Inc.

REV. D

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

FEATURES

PERFORMANCE

25 ns Instruction Cycle Time from 20 MHz Crystal

40 MIPS Sustained Performance

Single-Cycle Instruction Execution

Single-Cycle Context Switch

3-Bus Architecture Allows Dual Operand Fetches in

Multifunction Instructions

Power-Down Mode Featuring Low CMOS Standby

Low Power Dissipation in Idle Mode

INTEGRATION

ADSP-2100 Family Code Compatible, with Instruction

80K Bytes of On-Chip RAM, Configured as

Dual Purpose Program Memory for Both Instruction

Independent ALU, Multiplier/Accumulator, and Barrel

Two Independent Data Address Generators

Powerful Program Sequencer Provides

Programmable 16-Bit Interval Timer with Prescaler

128-Lead TQFP/128-Lead PQFP

SYSTEM INTERFACE

16-Bit Internal DMA Port for High Speed Access to

4 MByte Memory Interface for Storage of Data Tables

8-Bit DMA to Byte Memory for Transparent

I/O Memory Interface with 2048 Locations Supports

Programmable Memory Strobe and Separate I/O Memory

Programmable Wait State Generation

Two Double-Buffered Serial Ports with Companding

Automatic Booting of On-Chip Program Memory from

Six External Interrupts

13 Programmable Flag Pins Provide Flexible System

ICE-Port™ Emulator Interface Supports Debugging

@ 5.0 Volts

Every Instruction Cycle

Power Dissipation with 100 Cycle Recovery from

Power-Down Condition

Set Extensions

16K Words On-Chip Program Memory RAM

16K Words On-Chip Data Memory RAM

and Data Storage

Shifter Computational Units

Zero Overhead Looping

Conditional Instruction Execution

On-Chip Memory

and Program Overlays

Program and Data Memory Transfers

Parallel Peripherals

Space Permits “Glueless” System Design

Hardware and Automatic Data Buffering

Byte-Wide External Memory, e.g., EPROM, or

Through Internal DMA Port

Signaling

in Final Systems

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

GENERAL DESCRIPTION

The ADSP-2181 is a single-chip microcomputer optimized for

digital signal processing (DSP) and other high speed numeric

processing applications.

The ADSP-2181 combines the ADSP-2100 family base archi-

tecture (three computational units, data address generators and

a program sequencer) with two serial ports, a 16-bit internal

DMA port, a byte DMA port, a programmable timer, Flag I/O,

extensive interrupt capabilities, and on-chip program and data

memory.

The ADSP-2181 integrates 80K bytes of on-chip memory con-

figured as 16K words (24-bit) of program RAM, and 16K words

(16-bit) of data RAM. Power-down circuitry is also provided to

meet the low power needs of battery operated portable equip-

ment. The ADSP-2181 is available in 128-lead TQFP and 128-

lead PQFP packages.

In addition, the ADSP-2181 supports new instructions, which

include bit manipulations—bit set, bit clear, bit toggle, bit test—

new ALU constants, new multiplication instruction (x squared),

biased rounding, result free ALU operations, I/O memory trans-

fers and global interrupt masking for increased flexibility.

Fabricated in a high speed, double metal, low power, CMOS

process, the ADSP-2181 operates with a 25 ns instruction cycle

time. Every instruction can execute in a single processor cycle.

The ADSP-2181’s flexible architecture and comprehensive

instruction set allow the processor to perform multiple opera-

tions in parallel. In one processor cycle the ADSP-2181 can:

• Generate the next program address

• Fetch the next instruction

• Perform one or two data moves

• Update one or two data address pointers

• Perform a computational operation

DATA ADDRESS

GENERATORS

DAG 1

ALU

ARITHMETIC UNITS

ADSP-2100 BASE

ARCHITECTURE

DAG 2

MAC

FUNCTIONAL BLOCK DIAGRAM

SEQUENCER

SHIFTER

PROGRAM

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

PROGRAM MEMORY DATA

DATA MEMORY DATA

World Wide Web Site: http://www.analog.com

DSP Microcomputer

SPORT 0

PROGRAM

MEMORY

SERIAL PORTS

POWER-DOWN

CONTROL

MEMORY

SPORT 1

MEMORY

DATA

ADSP-2181

TIMER

PROGRAMMABLE

CONTROLLER

BYTE DMA

FLAGS

INTERNAL

I/O

PORT

DMA

DMA BUS

EXTERNAL

ADDRESS

EXTERNAL

DATA BUS

BUS

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