24LC256ISM Microchip Technology Inc., 24LC256ISM Datasheet

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24LC256ISM

Manufacturer Part Number
24LC256ISM
Description
SOP-8
Manufacturer
Microchip Technology Inc.
Datasheets

Specifications of 24LC256ISM

Date_code
09+
DEVICE SELECTION TABLE
FEATURES
• Low power CMOS technology
• 2-wire serial interface bus, I
• Cascadable for up to eight devices
• Self-timed ERASE/WRITE cycle
• 64-byte page-write mode available
• 5 ms max write-cycle time
• Hardware write protect for entire array
• Output slope control to eliminate ground bounce
• Schmitt trigger inputs for noise suppression
• 100,000 erase/write cycles guaranteed
• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• 8-pin PDIP and SOIC (208 mil) packages
• Temperature ranges:
DESCRIPTION
The Microchip Technology Inc. 24AA256/24LC256/
24FC256 (24XX256*) is a 32K x 8 (256K bit) Serial
Electrically Erasable PROM, capable of operation
across a broad voltage range (1.8V to 5.5V). It has
been developed for advanced, low power applications
such as personal communications or data acquisition.
This device also has a page-write capability of up to 64
bytes of data. This device is capable of both random
and sequential reads up to the 256K boundary. Func-
tional address lines allow up to eight devices on the
same bus, for up to 2M bit address space. This device
is available in the standard 8-pin plastic DIP and 8-pin
SOIC (208 mil) packages.
I
*24XX256 is used in this document as a generic part number for the 24AA256/24LC256/24FC256 devices.
M
2
C is a trademark of Philips Corporation.
100 kHz for V
100 kHz for E temperature range.
24AA256
24LC256
24FC256
1998 Microchip Technology Inc.
- Maximum write current 3 mA at 5.5V
- Maximum read current 400 µA at 5.5V
- Standby current 100 nA typical at 5.5V
- Industrial (I):
- Automotive (E):
Number
Part
CC
1.8-5.5V
2.5-5.5V
2.5-5.5V
Range
V
< 2.5V.
CC
256K Bit I
-40 C to
-40 C to +125 C
Frequency
Max Clock
400 kHz
400 kHz
2
C compatible
1 MHz
24AA256/24LC256/24FC256
+85 C
2
C
Ranges
Temp
I, E
I
I
CMOS Serial EEPROM
Preliminary
PACKAGE TYPE
BLOCK DIAGRAM
PDIP
SOIC
SDA
I/O
V
V
CONTROL
CC
SS
LOGIC
I/O
SCL
Vss
A0 A1 A2
V
A0
A1
A2
A0
A1
A2
SS
CONTROL
MEMORY
LOGIC
1
2
3
4
WP
1
2
3
4
XDEC
8
7
6
5
8
7
6
5
DS21203D-page 1
HV GENERATOR
PAGE LATCHES
R/W CONTROL
V
WP
SCL
SDA
Vcc
WP
SCL
SDA
SENSE AMP
CC
EEPROM
ARRAY
YDEC

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