AS7C1024B15JC Alliance Semiconductor, AS7C1024B15JC Datasheet

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AS7C1024B15JC

Manufacturer Part Number
AS7C1024B15JC
Description
SOJ32
Manufacturer
Alliance Semiconductor
Datasheet
March 2004
Logic block diagram
GND
Selection guide
Features
• Industrial and commercial temperatures
• Organization: 131,072 words x 8 bits
• High speed
• Low power consumption: ACTIVE
• Low power consumption: STANDBY
• 6T 0.18u CMOS technology
• Easy memory expansion with CE1, CE2, OE inputs
• TTL/LVTTL-compatible, three-state I/O
• 32-pin JEDEC standard packages
V
Maximum address access time
Maximum output enable access
time
Maximum Operating Current
Maximum CMOS standby Current
A0
A1
A2
A3
A4
A5
A6
A7
A8
3/26/04, v 1.2
- 10/12/15/20 ns address access time
- 5/6/7/8 ns output enable access time
- 605 mW / max @ 10 ns
- 55 mW / max CMOS
CC
Column decoder
512 x 256 x 8
(1,048,576)
Input buffer
Array
Control
circuit
Alliance Memory Inc
110
-10
10
10
5
5V 128K X 8 CMOS SRAM
WE
OE
CE1
CE2
I/O7
I/O0
100
-12
12
10
6
Pin arrangement
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
- 300 mil SOJ
- 400 mil SOJ
- 8 × 20mm TSOP 1
- 8 x 13.4mm sTSOP 1
®
CE2
A13
A15
V
A16
A14
A12
A11
WE
NC
A9
A8
CC
A7
A6
A5
A4
GND
I/O0
I/O1
I/O2
A16
A14
A12
32-pin (8 x 13.4mm) sTSOP1
NC
A7
A6
A5
A4
A3
A2
A1
A0
32-pin (8 x 20mm) TSOP I
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
-15
15
90
10
7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Copyright © Alliance Memory Inc. All rights reserved.
V
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
CC
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
-20
20
80
10
8
AS7C1024B
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
P. 1 of 9
Unit
mA
mA
ns
ns

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