74VCX16240MTD Fairchild Semiconductor, 74VCX16240MTD Datasheet
74VCX16240MTD
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74VCX16240MTD Summary of contents
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... CMOS power dissipation. Ordering Code: Order Number Package Number 74VCX16240MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol © ...
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Connection Diagram Functional Description The 74VCX16240 contains sixteen inverting buffers with 3-STATE outputs. The device is nibble (4 bits) controlled with each nibble functioning identically, but independent of each other. The control pins may be shorted together to obtain full ...
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Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage ( Outputs 3-STATED Outputs Active (Note 3) 0. Input Diode Current ( ...
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DC Electrical Characteristics Symbol Parameter V LOW Level Output Voltage OL I Input Leakage Current I I 3-STATE Output Leakage OZ I Power-OFF Leakage Current OFF I Quiescent Supply Current Increase in I per Input CC CC ...
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AC Electrical Characteristics Symbol Parameter t Propagation Delay PHL t PLH t Output Enable Time PZL t PZH t Output Disable Time PLZ t PHZ t Output to Output Skew OSHL t (Note 7) OSLH Note 6: For C 50 ...
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AC Loading and Waveforms (V TEST PLH PHL PZL PLZ PZH PHZ FIGURE 2. Waveform for Inverting and Non-Inverting Functions FIGURE 3. 3-STATE Output High Enable and Disable Times for Low ...
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AC Loading and Waveforms (V TEST PLH PHL PZL PLZ PZH PHZ FIGURE 6. Waveform for Inverting and Non-Inverting Functions FIGURE 7. 3-STATE Output High Enable and Disable Times for Low ...
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Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...