CY7C1370D200AXC Cypress Semiconductor Corporation., CY7C1370D200AXC Datasheet

CY7C1370D200AXC

Manufacturer Part Number

CY7C1370D200AXC

Description

TQFP-100

Manufacturer

Cypress Semiconductor Corporation.

Datasheet

1.CY7C1370D167AXI.pdf (28 pages)

Specifications of CY7C1370D200AXC

Date_code

07+

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Cypress Semiconductor Corporation

Document #: 38-05555 Rev. *F

Features

Logic Block Diagram-CY7C1370D (512K x 36)

• Pin-compatible and functionally equivalent to ZBT™

• Supports 250-MHz bus operations with zero wait states

• Internally self-timed output buffer control to eliminate

• Fully registered (inputs and outputs) for pipelined

• Byte Write capability

• 3.3V core power supply (V

• 3.3V/2.5V I/O power supply(V

• Fast clock-to-output times

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed writes

• Available in JEDEC-standard lead-free 100-pin TQFP,

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• Burst capability—linear or interleaved burst order

• “ZZ” Sleep Mode option and Stop Clock option

— Available speed grades are 250, 200 and 167 MHz

the need to use asynchronous OE

operation

— 2.6 ns (for 250-MHz device)

lead-free and non-lead-free 119-Ball BGA and 165-Ball

FBGA package

CEN

CLK

A0, A1, A

ADV/LD

MODE

CE1

CE2

CE3

WRITE ADDRESS

)

DDQ

ADDRESS

)

CONTROL

READ LOGIC

SLEEP

AND DATA COHERENCY

WRITE REGISTRY

•

CONTROL LOGIC

WRITE ADDRESS

ADV/LD

198 Champion Court

18-Mbit (512K x 36/1M x 18) Pipelined

BURST

LOGIC

A1'

A0'

SRAM with NoBL™ Architecture

DRIVERS

WRITE

Functional Description

The CY7C1370D and CY7C1372D are 3.3V, 512K x 36 and

1M x 18 Synchronous pipelined burst SRAMs with No Bus

Latency™ (NoBL™) logic, respectively. They are designed to

support unlimited true back-to-back Read/Write operations

with no wait states. The CY7C1370D and CY7C1372D are

equipped with the advanced (NoBL) logic required to enable

consecutive Read/Write operations with data being trans-

ferred on every clock cycle. This feature dramatically improves

the throughput of data in systems that require frequent

Write/Read transitions. The CY7C1370D and CY7C1372D are

pin compatible and functionally equivalent to ZBT devices.

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. The

clock input is qualified by the Clock Enable (CEN) signal,

which when deasserted suspends operation and extends the

previous clock cycle.

Write operations are controlled by the Byte Write Selects

(BW

and a Write Enable (WE) input. All writes are conducted with

on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. In order to avoid bus

contention, the output drivers are synchronously tri-stated

during the data portion of a write sequence.

–BW

•

MEMORY

ARRAY

INPUT

San Jose

for CY7C1370D and BW

CA 95134-1709

INPUT

Revised June 28, 2006

–BW

DQs

DQP

, CE

CY7C1370D

CY7C1372D

•

for CY7C1372D)

, CE

408-943-2600

) and an

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