GAL18V10B20LP Lattice Semiconductor Corp., GAL18V10B20LP Datasheet

GAL18V10B20LP

Manufacturer Part Number

GAL18V10B20LP

Description

DIP-20

Manufacturer

Lattice Semiconductor Corp.

Datasheet

1.GAL18V10B20LP.pdf (14 pages)

Specifications of GAL18V10B20LP

Date_code

04+

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Bonase Electronics (HK) Co., Limited

Part Number:

GAL18V10B20LP

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• HIGH PERFORMANCE E

• LOW POWER CMOS

• ACTIVE PULL-UPS ON ALL PINS

• E

• TEN OUTPUT LOGIC MACROCELLS

• PRELOAD AND POWER-ON RESET OF REGISTERS

• APPLICATIONS INCLUDE:

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

The GAL18V10, at 7.5 ns maximum propagation delay time, com-

bines a high performance CMOS process with Electrically Eras-

able (E

PLD. CMOS circuitry allows the GAL18V10 to consume much less

power when compared to its bipolar counterparts. The E

ogy offers high speed (<100ms) erase times, providing the ability

to reprogram or reconfigure the device quickly and efficiently.

By building on the popular 22V10 architecture, the GAL18V10

eliminates the learning curve usually associated with using a new

device architecture. The generic architecture provides maximum

design flexibility by allowing the Output Logic Macrocell (OLMC)

to be configured by the user. The GAL18V10 OLMC is fully com-

patible with the OLMC in standard bipolar and CMOS 22V10 de-

vices.

Unique test circuitry and reprogrammable cells allow complete AC,

DC, and functional testing during manufacture. As a result, Lattice

Semiconductor delivers 100% field programmability and function-

ality of all GAL products. In addition, 100 erase/write cycles and

data retention in excess of 20 years are specified.

18v10_04

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

Features

Description

— 7.5 ns Maximum Propagation Delay

— Fmax = 111 MHz

— 5.5 ns Maximum from Clock Input to Data Output

— TTL Compatible 16 mA Outputs

— UltraMOS

— 75 mA Typical Icc

— Reconfigurable Logic

— Reprogrammable Cells

— 100% Tested/100% Yields

— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

— Uses Standard 22V10 Macrocell Architecture

— Maximum Flexibility for Complex Logic Designs

— 100% Functional Testability

— DMA Control

— State Machine Control

— High Speed Graphics Processing

— Standard Logic Speed Upgrade

CELL TECHNOLOGY

) floating gate technology to provide a very flexible 20-pin

Advanced CMOS Technology

CMOS

TECHNOLOGY

technol-

Functional Block Diagram

Pin Configuration

I/CLK

I/O/Q

GAL18V10

GND

PLCC

Top View

I/CLK

I/O/Q

High Performance E

I/O/Q I/O/Q

Vcc

I/O/Q

Generic Array Logic™

GAL18V10

RESET

PRESET

I/CLK

I/O/Q

GND

OLMC

November 2003

18V10

DIP

GAL

CMOS PLD

I/O/Q

Vcc

I/O/Q

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