GAL26CV12B20LP Lattice Semiconductor Corp., GAL26CV12B20LP Datasheet

GAL26CV12B20LP

Manufacturer Part Number

GAL26CV12B20LP

Description

DIP-28

Manufacturer

Lattice Semiconductor Corp.

Datasheet

1.GAL26CV12B15LJI.pdf (17 pages)

Specifications of GAL26CV12B20LP

Date_code

06+

Current page: 1 of 17
Download datasheet (257Kb)

• HIGH PERFORMANCE E

• ACTIVE PULL-UPS ON ALL PINS

• LOW POWER CMOS

• E

• TWELVE OUTPUT LOGIC MACROCELLS

• PRELOAD AND POWER-ON RESET OF REGISTERS

• APPLICATIONS INCLUDE:

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

The GAL26CV12, at 7.5 ns maximum propagation delay time,

combines a high performance CMOS process with Electrically

Erasable (E

performance 28-pin PLD available on the market. E

offers high speed (<100ms) erase times, providing the ability to

reprogram or reconfigure the device quickly and efficiently.

Expanding upon the industry standard 22V10 architecture, the

GAL26CV12 eliminates the learning curve typically associated with

using a new device architecture. The generic architecture provides

maximum design flexibility by allowing the Output Logic Macrocell

(OLMC) to be configured by the user. The GAL26CV12 OLMC is

fully compatible with the OLMC in standard bipolar and CMOS

22V10 devices.

Unique test circuitry and reprogrammable cells allow complete AC,

DC, and functional testing during manufacture. As a result, Lattice

Semiconductor delivers100% field programmability and functionality

of all GAL products. In addition, 100 erase/write cycles and data

retention in excess of 20 years are specified.

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

26cv12_03

Features

Description

— 7.5 ns Maximum Propagation Delay

— Fmax = 142.8 MHz

— 4.5ns Maximum from Clock Input to Data Output

— TTL Compatible 16 mA Outputs

— UltraMOS

— 90 mA Typical Icc

— Reconfigurable Logic

— Reprogrammable Cells

— 100% Tested/100% Yields

— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

— Uses Standard 22V10 Macrocells

— Maximum Flexibility for Complex Logic Designs

— 100% Functional Testability

— DMA Control

— State Machine Control

— High Speed Graphics Processing

— Standard Logic Speed Upgrade

CELL TECHNOLOGY

) floating gate technology to provide the highest

Advanced CMOS Technology

CMOS

TECHNOLOGY

technology

Functional Block Diagram

Pin Configuration

VCC

I/CLK

GAL26CV12

Top View

PLCC

High Performance E

GAL26CV12

I/O/Q

GND

I/O/Q

Generic Array Logic™

PRESET

RESET

I/CLK

OLMC

Vcc

26CV12

GAL

DIP

CMOS PLD

June 2000

I/O/Q

INPUT

I/O/Q

GND

I/O/Q

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