GAL26V12C7LJ Lattice Semiconductor Corp., GAL26V12C7LJ Datasheet

GAL26V12C7LJ

Manufacturer Part Number

GAL26V12C7LJ

Description

PLCC

Manufacturer

Lattice Semiconductor Corp.

Datasheet

1.GAL26V12C15LP.pdf (16 pages)

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• HIGH PERFORMANCE E

• LOW POWER CMOS

• E

• TWELVE OUTPUT LOGIC MACROCELLS

• PRELOAD AND POWER-ON RESET OF REGISTERS

• APPLICATIONS INCLUDE:

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

The GAL26V12, at 7.5ns maximum propagation delay time, com-

bines a high performance CMOS process with Electrically Eras-

able (E

ance available of any 26V12 device on the market. E

ogy offers high speed (<100ms) erase times, providing the ability

to reprogram or reconfigure the device quickly and efficiently.

The generic architecture provides maximum design flexibility by

allowing the Output Logic Macrocell (OLMC) to be configured by

the user. The GAL26V12 is fully function/fuse map/parametric

compatible with other 26V12 devices.

Unique test circuitry and reprogrammable cells allow complete

AC, DC, and functional testing during manufacture. As a result,

LATTICE is able to guarantee 100% field programmability and

functionality of all GAL

erase/rewrite cycles.

tor Corp. The specifications herein are subject to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 N.E. Moore Ct., Hillsboro, Oregon 97124 U.S.A.

Tel. (503) 268-8000 or 1-800-LATTICE; FAX (503) 268-8556

FEATURES

— 7.5 ns Maximum Propagation Delay

— Fmax = 142.8 MHz

— 4.5 ns Maximum from Clock Input to Data Output

— TTL Compatible 16 mA Outputs

— UltraMOS

— 90 mA Typical Icc

— Reconfigurable Logic

— Reprogrammable Cells

— 100% Tested/Guaranteed 100% Yields

— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

— Maximum Flexibility for Complex Logic Designs

— 100% Functional Testability

— DMA Control

— State Machine Control

— High Speed Graphics Processing

— Standard Logic Speed Upgrade

DESCRIPTION

CELL TECHNOLOGY

) floating gate technology to provide the highest perform-

Advanced CMOS Technology

products. LATTICE also guarantees 100

CMOS

TECHNOLOGY

CMOS and UltraMOS are registered trademarks of Lattice Semiconductor Corp. Generic Array Logic is a trademark of Lattice Semiconduc-

technol-

VCC

INPUT/CLK 2

FUNCTIONAL BLOCK DIAGRAM

PACKAGE DIAGRAMS

I/CLK 1

INPUT

GAL26V12

Top View

PLCC

High Performance E

I/O/Q

GND

I/O/Q

Generic Array Logic

GAL26V12

RESET

PRESET

I/CLK1

I/CLK2

OLMC 10

OLMC 11

OLMC 4

OLMC 5

OLMC 0

OLMC 6

OLMC 7

OLMC 8

OLMC 9

OLMC 1

OLMC 2

OLMC 3

Vcc

November 2000

26V12

CMOS PLD

GAL

DIP

I/O/Q

INPUT

I/O/Q

GND

I/O/Q

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