GAL6001B30LP Lattice Semiconductor Corp., GAL6001B30LP Datasheet

GAL6001B30LP

Manufacturer Part Number

GAL6001B30LP

Description

DIP-24

Manufacturer

Lattice Semiconductor Corp.

Datasheet

1.GAL6001B30LP.pdf (15 pages)

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• HIGH PERFORMANCE E

• LOW POWER CMOS

• E

• UNPRECEDENTED FUNCTIONAL DENSITY

• HIGH-LEVEL DESIGN FLEXIBILITY

• APPLICATIONS INCLUDE:

Using a high performance E

Semiconductor has produced a next-generation programmable

logic device, the GAL6001. Having an FPLA architecture, known

for its superior flexibility in state-machine design, the GAL6001

offers a high degree of functional integration and flexibility in a 24-

pin, 300-mil package.

The GAL6001 has 10 programmable Output Logic Macrocells

(OLMC) and 8 programmable Buried Logic Macrocells (BLMC). In

addition, there are 10 Input Logic Macrocells (ILMC) and 10

I/O Logic Macrocells (IOLMC). Two clock inputs are provided for

independent control of the input and output macrocells.

Advanced features that simplify programming and reduce test time,

coupled with E

programmability, and functionality testing of each GAL6001 during

manufacture. As a result, Lattice Semiconductor delivers 100% field

programmability and functionality of all GAL products. In addition,

100 erase/write cycles and data retention in excess of 20 years are

specified.

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

6001_02

Features

Description

— 30ns Maximum Propagation Delay

— 27MHz Maximum Frequency

— 12ns Maximum Clock to Output Delay

— TTL Compatible 16mA Outputs

— UltraMOS

— 90mA Typical Icc

— Reconfigurable Logic

— Reprogrammable Cells

— 100% Tested/100% Yields

— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

— 78 x 64 x 36 FPLA Architecture

— 10 Output Logic Macrocells

— 8 Buried Logic Macrocells

— 20 Input and I/O Logic Macrocells

— Asynchronous or Synchronous Clocking

— Separate State Register and Input Clock Pins

— Functional Superset of Existing 24-pin PAL

— Sequencers

— State Machine Control

— Multiple PLD Device Integration

CELL TECHNOLOGY

and FPLA Devices

CMOS reprogrammable cells, enable 100% AC, DC,

Advanced CMOS Technology

CMOS

CMOS technology, Lattice

TECHNOLOGY

Functional Block Diagram

Macrocell Names

Pin Names

Pin Configuration

ILMC

IOLMC I/O LOGIC MACROCELL

BLMC

OLMC

ICLK

OCLK

- I

INPUTS

2-11

CLOCK

INPUT

{

INPUT LOGIC MACROCELL

BURIED LOGIC MACROCELL

OUTPUT LOGIC MACROCELL

INPUT

INPUT CLOCK

OUTPUT CLOCK

GAL6001

Top View

ILMC

PLCC

BLMC

High Performance E

ICLK

I/O/Q

AND

Generic Array Logic™

I/O/Q

GND

GAL6001

OUTPUT

ENABLE

I/ICLK

GND

BIDIRECTIONAL

POWER (+5)

GROUND

OLMC

OCLK

CMOS FPLA

6001

DIP

GAL

IOLMC

July 1997

{

OUTPUTS

OUTPUT

14 - 23

CLOCK

Vcc

I/O/Q

OCLK

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