GAL6002B20LP Lattice Semiconductor Corp., GAL6002B20LP Datasheet

GAL6002B20LP

Manufacturer Part Number

GAL6002B20LP

Description

DIP-24

Manufacturer

Lattice Semiconductor Corp.

Datasheet

1.GAL6002B20LP.pdf (16 pages)

Specifications of GAL6002B20LP

Date_code

04+

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• HIGH PERFORMANCE E

• ACTIVE PULL-UPS ON ALL PINS

• LOW POWER CMOS

• E

• UNPRECEDENTED FUNCTIONAL DENSITY

• HIGH-LEVEL DESIGN FLEXIBILITY

• APPLICATIONS INCLUDE:

Having an FPLA architecture, the GAL6002 provides superior

flexibility in state-machine design. The GAL6002 offers the highest

degree of functional integration, flexibility, and speed currently

available in a 24-pin, 300-mil package. E

high speed (<100ms) erase times, providing the ability to reprogram

or reconfigure the device quickly and efficiently.

The GAL6002 has 10 programmable Output Logic Macrocells

(OLMC) and 8 programmable Buried Logic Macrocells (BLMC). In

addition, there are 10 Input Logic Macrocells (ILMC) and 10

I/O Logic Macrocells (IOLMC). Two clock inputs are provided for

independent control of the input and output macrocells.

Unique test circuitry and reprogrammable cells allow complete AC,

DC, and functional testing during manufacturing. As a result, Lattice

Semiconductor delivers 100% field programmability and

functionality of all GAL products. In addition, 100 erase/write cycles

and data retention in excess of 20 years are specified.

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

6002_02

Features

Description

— 15ns Maximum Propagation Delay

— 75MHz Maximum Frequency

— 6.5ns Maximum Clock to Output Delay

— TTL Compatible 16mA Outputs

— UltraMOS

— 90mA Typical Icc

— Reconfigurable Logic

— Reprogrammable Cells

— 100% Tested/100% Yields

— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

— 78 x 64 x 36 FPLA Architecture

— 10 Output Logic Macrocells

— 8 Buried Logic Macrocells

— 20 Input and I/O Logic Macrocells

— Asynchronous or Synchronous Clocking

— Separate State Register and Input Clock Pins

— Functional Superset of Existing 24-pin PAL

— Sequencers

— State Machine Control

— Multiple PLD Device Integration

CELL TECHNOLOGY

and FPLA Devices

Advanced CMOS Technology

CMOS

TECHNOLOGY

CMOS technology offers

Functional Block Diagram

Macrocell Names

PinNames

Pin Configuration

ILMC

IOLMC I/O LOGIC MACROCELL

BLMC

OLMC

ICLK

OCLK

INPUTS

2-11

CLOCK

- I

INPUT

{

INPUT LOGIC MACROCELL

BURIED LOGIC MACROCELL

OUTPUT LOGIC MACROCELL

INPUT

INPUT CLOCK

OUTPUT CLOCK

GAL6002

Top View

ILMC

PLCC

BLMC

High Performance E

ICLK

I/O/Q

AND

Generic Array Logic™

I/O/Q

GND

GAL6002

OUTPUT

ENABLE

I/ICLK

BIDIRECTIONAL

POWER (+5V)

GROUND

GND

OLMC

OCLK

CMOS FPLA

6002

GAL

DIP

IOLMC

July 1997

{

OUTPUTS

Vcc

I/O/Q

OCLK

OUTPUT

14 - 23

CLOCK

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