IDT54FCT833ADB Integrated Device Technology, Inc., IDT54FCT833ADB Datasheet
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IDT54FCT833ADB
Manufacturer Part Number
IDT54FCT833ADB
Description
CDIP24
Manufacturer
Integrated Device Technology, Inc.
Datasheet
1.IDT74FCT833A.pdf
(8 pages)
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FEATURES:
• Equivalent to AMD’s Am29833 bipolar parity bus
• High-speed bidirectional bus transceiver for processor-
• IDT54/74FCT833A equivalent to Am29833A speed and
• IDT54/74FCT833B 30% faster than Am29833A
• Buffered direction and three-state controls
• Error flag with open-drain output
• I
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than AMD’s
• Available in plastic DIP, CERDIP, LCC and SOIC
• Product available in Radiation Tolerant and Radiation
• Military product compliant to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1992 Integrated Device Technology, Inc.
Integrated Device Technology, Inc.
transceiver in pinout/function, speed and output drive
over full temperature and voltage supply extremes
organized devices
output drive
bipolar Am29800 series (5 A max.)
Enhanced versions
OL
CLR
CLK
= 48mA (commercial) and 32mA (military)
OE
OE
T
R
R
I
8
S
PARITY TREE
FAST CMOS
PARITY BUS
TRANSCEIVER
8
9-BIT
MUX
9
8
7.21
P
DESCRIPTION:
transceivers designed for two-way communications. They
each contain an 8-bit data path from the R (port) to the T (port),
an 8-bit data path from the T (port) to the R (port), and a 9-bit
parity checker/generator. The error flag can be clocked and
stored in a register and read at the
(
port outputs to the high-impedance state so that the device
can drive bus lines directly. In addition,
used to force a parity error by enabling both lines
simultaneously. This transmission of inverted parity gives the
designer more system diagnostic capability. The devices are
specified at 48mA and 32mA output sink current over the
commercial and military temperature ranges, respectively.
CLR
The IDT54/74FCT833s are high-performance bus
The output enables
) input is used to clear the error flag register.
8
D
CP
CLR
T
PARITY
I
OE
Q
Q
T
and
OE
IDT54/74FCT833A
IDT54/74FCT833B
R
ERR
are used to force the
OE
output. The clear
R
and
ERR
2557 drw 01
OE
MAY 1992
T
1
DSC-4621/2
can be