ISPGAL22V10C15LJN Lattice Semiconductor Corp., ISPGAL22V10C15LJN Datasheet

ISPGAL22V10C15LJN

Manufacturer Part Number

ISPGAL22V10C15LJN

Description

PLCC-28

Manufacturer

Lattice Semiconductor Corp.

Datasheet

1.ISPGAL22V10C10LJN.pdf (14 pages)

Specifications of ISPGAL22V10C15LJN

Date_code

05+

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• IN-SYSTEM PROGRAMMABLE™ (5-V ONLY)

• HIGH PERFORMANCE E

• ACTIVE PULL-UPS ON ALL LOGIC INPUT AND I/O PINS

• COMPATIBLE WITH STANDARD 22V10 DEVICES

• E

• TEN OUTPUT LOGIC MACROCELLS

• APPLICATIONS INCLUDE:

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

• LEAD-FREE PACKAGE OPTIONS

The ispGAL22V10, at 7.5ns maximum propagation delay time,

combines a high performance CMOS process with Electrically Eras-

able (E

system programmable 22V10 device. E

speed (<100ms) erase times, providing the ability to reprogram or

reconfigure the device quickly and efficiently.

The generic architecture provides maximum design flexibility by al-

lowing the Output Logic Macrocell (OLMC) to be configured by the

user. The ispGAL22V10 is fully function/fuse map/parametric com-

patible with standard bipolar and CMOS 22V10 devices. The stan-

dard PLCC package provides the same functional pinout as the

standard 22V10 PLCC package with No-Connect pins being used

for the ISP interface signals.

Unique test circuitry and reprogrammable cells allow complete AC,

DC, and functional testing during manufacture. As a result, Lat-

tice Semiconductor delivers 100% field programmability and func-

tionality of all GAL products. In addition, 10,000 erase/write cycles

and data retention in excess of 20 years are specified.

isp22v10_04

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

Features

Description

— 4-Wire Serial Programming Interface

— Minimum 10,000 Program/Erase Cycles

— Built-in Pull-Down on SDI Pin Eliminates Discrete

— 7.5 ns Maximum Propagation Delay

— Fmax = 111 MHz

— 5 ns Maximum from Clock Input to Data Output

— UltraMOS

— Fully Function/Fuse-Map/Parametric Compatible

— In-System Programmable Logic

— 100% Tested/100% Yields

— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

— Maximum Flexibility for Complex Logic Designs

— DMA Control

— State Machine Control

— High Speed Graphics Processing

— Software-Driven Hardware Configuration

CELL TECHNOLOGY

Resistor on Board (ispGAL22V10C Only)

with Bipolar and CMOS 22V10 Devices

) floating gate technology to provide the industry's first in-

Advanced CMOS Technology

CMOS

TECHNOLOGY

technology offers high

MODE

Functional Block Diagram

Pin Configuration

MODE

SCLK

SDO

SDI

1 1

In-System Programmable E

1 2

ispGAL22V10

PROGRAMMING

I/CLK

Top View

LOGIC

1 4

PLCC

1 6

2 8

ispGAL22V10

1 8

2 6

2 3

2 1

2 5

1 9

Generic Array Logic™

I/O/Q

SDO

I/O/Q

MODE

SCLK

I/CLK

GND

PRESET

RESET

OLMC

Top View

ispGAL

SSOP

22V10

CMOS PLD

August 2004

I/O/Q

Vcc

I/O/Q

SDO

I/O/Q

SDI

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