ISPGDS227J Lattice Semiconductor Corp., ISPGDS227J Datasheet

ISPGDS227J

Manufacturer Part Number

ISPGDS227J

Description

PLCC28

Manufacturer

Lattice Semiconductor Corp.

Datasheet

1.ISPGDS227J.pdf (8 pages)

Specifications of ISPGDS227J

Date_code

01+

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• HIGH-SPEED SWITCH MATRIX

• FLEXIBLE I/O MACROCELL

• IN-SYSTEM PROGRAMMABLE (5-VOLT ONLY)

• E

• APPLICATIONS INCLUDE:

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

The Lattice Semiconductor ispGDS™ family is an ideal solution

for reconfiguring system signal routing or replacing DIP switches

used for feature selection. With today’s demands for customer

ease of use, there is a need for hardware which is easily

reconfigured electronically without dismantling the system. The

ispGDS devices address this challenge by replacing conventional

switches with a software configurable solution. Since each I/O pin

can be set to an independent logic level, the ispGDS devices can

replace most DIP switch functions with about half the pin count,

and without the need for additional pull-up resistors. In addition

to DIP switch replacement, the ispGDS devices are useful as

signal routing cross-matrix switches. This is the only non-volatile

device on the market which can provide this flexibility.

With a maximum tpd of 7.5ns, and a typical active Icc of only 25

mA, these devices provide maximum performance at very low

power levels. The ispGDS devices may be programmed in-sys-

tem, using 5 volt only signals, through a simple 4-wire program-

ming interface. The ispGDS devices are manufactured using

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268--8037; http://www.latticesemi.com

ispgds_03

Features

Description

— 7.5 ns Maximum Propagation Delay

— Typical Icc = 25 mA

— UltraMOS

— Any I/O Pin Can be Input, Output, or Fixed

— Programmable Output Polarity

— Multiple Outputs Can be Driven by One Input

— Programming Time of Less Than One Second

— 4-Wire Programming Interface

— Minimum 10,000 Program/Erase Cycles

— Non-Volatile Reprogrammable Cells

— 100% Tested/100% Yields

— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

— Software-Driven Hardware Configuration

— Multiple DIP Switch Replacement

— Software Configuration of Add-In Boards

— Configurable Addressing of I/O Boards

— Multiple Clock Source Selection

— Cross-Matrix Switch

CELL TECHNOLOGY

TTL High or Low

Advanced CMOS Technology

Lattice Semiconductor’s advanced non-volatile E

which combines CMOS with Electrically Erasable (E

technology. High speed erase times (<100ms) allow the devices

to be reprogrammed quickly and efficiently.

Each I/O macrocell can be configured as an input, an inverting

or non-inverting output, or a fixed TTL high or low output. Any

I/O pin can be driven by any other I/O pin in the opposite bank.

A single input can drive one or more outputs in the opposite bank,

allowing a signal (such as a clock) to be distributed to multiple des-

tinations on the board, under software control. The I/Os accept

and drive TTL voltage levels.

Unique test circuitry and reprogrammable cells allow complete

AC, DC, and functional testing during manufacture. As a result,

Lattice Semiconductor is able to deliver 100% field programma-

bility and functionality of all Lattice Semiconductor products. In

addition, 10,000 erase/write cycles and data retention in excess

of 20 years are specified.

Functional Block Diagram (ispGDS22)

A10

I/O Cell

Switch

Matrix

I/O Cell

ispGDS22/14

Closed only when C0=1 and C1=0

in-system programmable

Vcc

PROGRAMMABLE

Generic Digital Switch

SWITCH MATRIX

0 1

1 0

1 1

0 0

4:1 MUX

November 2003

CMOS process

Bank B

) floating gate

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