ISPGDX1607Q208 Lattice Semiconductor Corp., ISPGDX1607Q208 Datasheet

ISPGDX1607Q208

Manufacturer Part Number

ISPGDX1607Q208

Description

QFP208

Manufacturer

Lattice Semiconductor Corp.

Datasheet

1.ISPGDX1607Q208.pdf (25 pages)

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• IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL

• HIGH PERFORMANCE E

• ispGDX OFFERS THE FOLLOWING ADVANTAGES

• FLEXIBLE ARCHITECTURE

• DESIGN SUPPORT THROUGH LATTICE’S ispGDX

are subject to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

ispgdx_08

Features

CROSSPOINT FAMILY

— Advanced Architecture Addresses Programmable

— Three Device Options: 80 to 160 Programmable I/O

— “Any Input to Any Output” Routing

— Fixed HIGH or LOW Output Option for Jumper/DIP

— Space-Saving TQFP, PQFP and BGA Packaging

— Dedicated IEEE 1149.1-Compliant Boundary Scan

— PCI Compliant Output Drive

— 5V Power Supply

— 5.0ns Input-to-Output/5.0ns Clock-to-Output Delay

— Low-Power: 40mA Quiescent Icc

— Balanced 24mA Output Buffers with Programmable

— Schmitt Trigger Inputs for Noise Immunity

— Electrically Erasable and Reprogrammable

— Non-Volatile E

— 100% Tested

— In-System Programmable

— Lattice ISP or JTAG Programming Interface

— Only 5V Power Supply Required

— Change Interconnects in Seconds

— Reprogram Soldered Devices

— Combinatorial/Latched/Registered Inputs or Outputs

— Individual I/O Tri-state Control with Polarity Control

— Dedicated Clock Input Pins (two or four) or

— Up to 4:1 Dynamic Path Selection

— Programmable Output Pull-up Resistors

— Outputs Tri-state During Power-up (“Live Insertion”

DEVELOPMENT SOFTWARE

— MS Windows or NT / PC-Based or Sun O/S

— Easy Text-Based Design Entry

— Automatic Signal Routing

— Program up to 100 ISP Devices Concurrently

— Simulator Netlist Generation for Easy Board-Level

PCB Interconnect, Bus Interface Integration and

Jumper/Switch Replacement

Pins

Switch Emulation

Test

Slew Rate Control

Programmable Clocks from I/O Pins (from 20 up to

40)

Friendly)

Simulation

CMOS Technology

CMOS

TECHNOLOGY

The ispGDX architecture provides a family of fast, flexible

programmable devices to address a variety of system-

level digital signal routing and interface requirements

including:

The ispGDX Family consists of three members with 80,

120 and 160 Programmable I/Os. These devices are

available in packages ranging from the 100-pin TQFP to

the 208-pin PQFP. The devices feature fast operation,

with input-to-output signal delays (Tpd) of 5ns and clock-

to-output delays of 5ns.

The architecture of the devices consists of a series of

programmable I/O cells interconnected by a Global Rout-

Functional Block Diagram

Description

Boundary

• Multi-Port Multiprocessor Interfaces

• Wide Data and Address Bus Multiplexing

• Programmable Control Signal Routing

• Board-Level PCB Signal Routing for Prototyping or

Control

Scan

(e.g. 4:1 High-Speed Bus MUX)

(e.g. Interrupts, DMAREQs, etc)

Programmable Bus Interfaces

Cells

ispGDX

I/O

Generic Digital Crosspoint

Global Routing

In-System Programmable

I/O Pins D

I/O Pins B

(GRP)

Pool

Family

Cells

I/O

August 2000

Control

ISP

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