ISPPACPOWR1208P101TN44I Lattice Semiconductor Corp., ISPPACPOWR1208P101TN44I Datasheet

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ISPPACPOWR1208P101TN44I

Manufacturer Part Number
ISPPACPOWR1208P101TN44I
Description
QFP44
Manufacturer
Lattice Semiconductor Corp.
Datasheet

Specifications of ISPPACPOWR1208P101TN44I

Date_code
07+
February 2005
Features
■ Monitor and Control Multiple Power
■ Precision Analog Comparators for
■ Embedded PLD for Sequence Control
■ Embedded Programmable Timers
■ Embedded Oscillator
■ Programmable Output Configurations
■ 2.7V to 5.5V Supply Range
© 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other
brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without
notice.
www.latticesemi.com
Supplies
Monitoring
• Simultaneously monitors up to 12 power supplies
• Sequence controller for power-up conditions
• Provides eight output control signals
• Programmable digital and analog circuitry
• 12 analog comparators for monitoring
• 384 programmable threshold levels spanning
• 0.5% precision
• Other user-defined voltages possible
• 80mV near-ground threshold for power-off
• Each comparator independently configurable
• Eight direct comparator outputs
• Digital filter on comparator outputs
• Implements state machine and input conditional
• In-System Programmable (ISP™) through JTAG
• Input synchronizers
• 4 Programmable 8-bit timers (32µs to 524ms)
• Programmable time delay between multiple
• Built-in clock generator, 1MHz
• Programmable clock frequency
• Programmable timer pre-scaler
• External clock support
• Four digital outputs for logic and power supply
• Four fully programmable gate driver outputs for
• Expandable with ispMACH™ 4000 CPLD
• In-system programmable at 3.0V to 5.5V
• Industrial temperature range: -40°C to +85°C
• 44-pin TQFP package
0.68V to 5.93V
detect
events
and on-chip E
power supply ramp-up and wait statements
control
FET control, or programmable as four additional
digital outputs
2
CMOS
®
1
ispPAC-POWR1208P1
Application Block Diagram
Description
The Lattice ispPAC-POWR1208P1 incorporates both in-
system programmable logic and in-system programma-
ble analog circuits to perform special functions for
power supply sequencing and monitoring. The ispPAC-
POWR1208P1 device has the capability to be config-
ured through software to control up to eight outputs for
power supply sequencing and 12 comparators monitor-
ing supply voltage limits, along with four digital inputs for
interfacing to other control circuits or digital logic. Once
configured, the design is downloaded into the device
through a standard JTAG interface. The circuit configu-
ration and routing are stored in non-volatile E
PAC-Designer,
software package gives users the ability to design and
simulate logic and sequences that control the power
supplies or FET driver circuits. The user has control
over timing functions, programmable logic functions and
comparator threshold values as well as I/O configura-
tions.
Sequencing Controller and Precision Monitor
V
Primary
Primary
Primary
Primary
DD
In-System Programmable Power Supply
+
+
+
+
-
-
-
-
VMON1
VMON2
VMON3
VMON4
VMON5
VMON6
VMON7
VMON8
VMON9
IN1
IN2
IN3
IN4
VMON10
VMON11
VMON12
RESET
CLK
12 Analog Inputs
DC/DC
Supply
Supply
DC/DC
DC/DC
Supply
DC/DC
Supply
ispPAC-POWR1208P1
Power Sequence
®
Gnd
Gnd
Gnd
Gnd
Controller
+
+
+
+
®
an easy-to-use Windows-compatible
+1.0V
+3.3V
+2.5V
+5V
10uF
VDD VDDINP
HVOUT1
HVOUT2
HVOUT3
HVOUT4
Comp1
Comp2
Comp3
Comp4
Comp5
Comp6
Comp7
Comp8
CREF
OUT5
OUT6
OUT7
OUT8
POR
0.1uF
R
R
R
R
G
G
G
G
0.1uF
3.3V
3.3V
DC/DC Supply
or Regulator
OE/EN
DC/DC Supply
or Regulator
OE/EN
EN
EN
Data Sheet
Circuits
Circuits
Circuits
Circuits
1208p1_01
+3.3V
+2.5V
Digital
Digital
+5V
+1V
Logic
Logic
2
CMOS.

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