M4A5643210JC Lattice Semiconductor Corp., M4A5643210JC Datasheet

M4A5643210JC

Manufacturer Part Number

M4A5643210JC

Description

PLCC-44

Manufacturer

Lattice Semiconductor Corp.

Datasheet

1.M4A5643210JC.pdf (3 pages)

Specifications of M4A5643210JC

Date_code

04+

Current page: 1 of 3
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The ispMACH 4A Family from Lattice offers an excep-

tionally flexible architecture and delivers a superior

Complex Programmable Logic Device (CPLD) solution

of easy-to-use silicon products and software tools. The

overall benefits for users are a guaranteed and predict-

able CPLD solution, faster time-to-market, greater

flexibility and lower cost. The ispMACH 4A devices offer

densities ranging from 32 to 512 macrocells with 100%

utilization and 100% pinout retention. The ispMACH 4A

Family offers 5V and 3.3V operation.

ispMACH 4A products are 5V or 3.3V in-system program-

mable through the JTAG (IEEE Standard 1149.1)

interface. JTAG boundary scan testing allows product

testability on automated test equipment for device con-

nectivity.

All ispMACH 4A Family members deliver First-Time-

Fit™ and easy system integration with pin-out retention

after any design change and refit. For both 3.3V and 5V

operation, ispMACH 4A products can deliver guaranteed

fixed timing as fast as 5ns tpd and 182MHz fcnt through

the Speedlocking™ feature when using up to 20 product

terms per output.

The ispMACH 4A Family offers 21 density-I/O combina-

tions in Thin Quad Flat Pack (TQFP), Plastic Quad

Flatpack (PQFP), Plastic Leaded Chip Carrier (PLCC),

Ball Grid Array (BGA), Fine-pitch BGA (fpBGA) and Chip

Array BGA (caBGA) packages ranging from 44 to 388

pins. It also offers I/O safety features for mixed-voltage

designs so that the 3.3V device can accept 5V inputs, and

5V devices do not overdrive 3.3V inputs. Additional

features include Bus-Friendly inputs and I/Os, a pro-

grammable power-down mode for extra power savings

and individual output slew rate control for the highest

speed transition or for the lowest noise transition. Tables

1 and 2 describe the Family attributes.

ispMACH 4A Family

introm4a_03

Introduction

5.0ns Pin-to-Pin Delay; 182 MHz System Perfor-

mance

3.3V and 5V Versions; Safe for Mixed Supply

Voltage System Design

32 to 512 Macrocells; 1,250-20,000 PLD Gates

Speedlocking Performance; Guaranteed Fixed

Timing

ispMACH Development Tools

The ispMACH 4A Family is ideal for seamless integration

into a wide variety of system environments. It provides

many features to support system integration: 3.3V sup-

port at all densities and 5V support on selected densities;

mixed voltage support with 3.3V safety and 5V tolerance;

hot-socketing for board-edge and multiple power supply

applications; programmable pull-up or Bus-Friendly in-

puts and I/Os to hold inputs in known states; and JTAG

in-system programmability and test for rapid prototyping

and efficient manufacturing.

Each ispMACH 4A device consists of multiple PAL

blocks interconnected by a programmable central switch

matrix (CSM). Input switch matrices (ISMs) enhance

routability by providing input signals with alternative

paths into the CSM and output switch matrices (OSMs)

assign macrocell outputs to I/O pins. Each PAL block

consists of 16 macrocells with 33 to 36 inputs.

The ispMACH 4A devices feature a Speedlocking archi-

tecture that provides speed performance as fast as 5ns

tpd with up to 20 product terms per output independent of

routing and product term usage. Speedlocking delivers

ispMACH 4A Overview

ispMACH 4A Family

Low Power Consumption

Excellent Routability and Pin-Locking

Hot-Socketing Capability

Programmable Bus Friendly or Pull-up I/Os

IEEE 1149.1 Boundary Scan Testable

ispJTAG™ In-System Programmable

Commercial and Industrial Temperature Ranges

ispLEVER™ Systems for PC and Lattice

UNIX-Based Design Tools

Tightly Integrated with Leading CAE Vendors’

Tools

Productivity Enhancing Static Timing Analyzer,

Physical Viewer and Explore Tools

VHDL, Verilog-HDL, ABEL, State Machine and

Schematic Entry

Timing and Functional Simulators

Comprehensive ISP Programming Tools

Windows

Windows NT

UNIX Platforms

Introduction to

XP, Windows 2000, Windows 98,

, Solaris and Hewlett-Packard

February 2002

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