MC54HC366J Motorola, MC54HC366J Datasheet

MC54HC366J

Manufacturer Part Number

MC54HC366J

Description

CDIP

Manufacturer

Motorola

Datasheet

1.MC54HC366J.pdf (5 pages)

Specifications of MC54HC366J

Date_code

07+

Current page: 1 of 5
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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Hex 3-State Inverting Buffer

with Common Enables

High–Performance Silicon–Gate CMOS

are compatible with standard CMOS outputs; with pullup resistors, they are

compatible with LSTTL outputs.

common active–low Output Enables. When either of the enables is high, the

buffer outputs are placed into high–impedance states. The HC366 has

inverting outputs.

10/95

Motorola, Inc. 1995

The MC54/74HC366 is identical in pinout to the LS366. The device inputs

This device is a high–speed hex buffer with 3–state outputs and two

Output Drive Capability: 15 LSTTL Loads

Outputs Directly Interface to CMOS, NMOS, and TTL

Operating Voltage Range: 2 to 6 V

Low Input Current: 1 A

High Noise Immunity Characteristic of CMOS Devices

In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

Chip Complexity: 78 FETs or 19.5 Equivalent Gates

OUTPUT ENABLE 1 1

OUTPUT ENABLE 2

LOGIC DIAGRAM

PIN 16 = V CC

PIN 8 = GND

REV 6

MC54/74HC366

X = don’t care

Z = high impedance

Enable

ENABLE 1

OUTPUT

MC54HCXXXJ

MC74HCXXXN

ORDERING INFORMATION

GND

PIN ASSIGNMENT

FUNCTION TABLE

Inputs

Enable

CERAMIC PACKAGE

PLASTIC PACKAGE

CASE 620–10

CASE 648–08

N SUFFIX

J SUFFIX

Ceramic

Plastic

V CC

OUTPUT

ENABLE 2

Output

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