MC14007UBCPG ON Semiconductor, MC14007UBCPG Datasheet - Page 5

• Manufacturer Part Number: MC14007UBCPG
• Description: IC INVERTER DUAL COMP 14DIP
• Manufacturer: ON Semiconductor
• Series: 4000Br

Specifications of MC14007UBCPG

• Logic Type: Configurable Multiple Function
• Number Of Circuits: 2
• Number Of Inputs: 1
• Schmitt Trigger Input: No
• Output Type: Single-Ended
• Current - Output High, Low: 10mA, 10mA
• Voltage - Supply: 3 V ~ 18 V
• Operating Temperature: -55°C ~ 125°C
• Mounting Type: Through Hole
• Package / Case: 14-DIP (0.300", 7.62mm)
• Logic Family: MC140
• Number Of Channels Per Chip: Triple
• Polarity: Inverting
• Supply Voltage (max): 18 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• High Level Output Current: - 4.2 mA (Min)
• Input Bias Current (max): 1 uA
• Low Level Output Current: 4.2 mA (Min)
• Minimum Operating Temperature: - 55 C
• Propagation Delay Time: 125 ns @ 5 V or 75 ns @ 10 V or 55 ns @ 15 V
• Number Of Lines (input / Output): 3 / 3
• Output Current: 10mA
• No. Of Inputs: 1
• Supply Voltage Range: 3V To 18V
• Logic Case Style: DIP
• No. Of Pins: 14
• Operating Temperature Range: -55°C To +125°C
• Filter Terminals: DIP
• Rohs Compliant: Yes
• Family Type: 4000 CMOS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MC14007UBCPGOS

Figures 1, 6, and 7 are a few examples of the device flexibility.
The MC14007UB dual pair plus inverter, which has access to all its elements offers a number of unique circuit applications.
GENERATOR
DISABLE 3
DISABLE 6
PULSE
INPUT 10
X = Don’t Care
INPUT
500 mF
Figure 6. 3−State Buffer
X
1
0
Figure 5. Switching Time and Power Dissipation Test Circuit and Waveforms
V
in
DISABLE
7
V
I
D
0
0
1
DD
+V
14
V
DD
SS
2
1
11
9
8
7
0.01 mF
CERAMIC
OUTPUT
12 OUTPUT
OPEN
0
1
C
L
V
out
http://onsemi.com
APPLICATIONS
5
Substrates of P−Channel devices internally connected to V
Substrates of N−Channel devices internally connected to V
Figure 7. AOI Functions Using Tree Logic
V
V
out
in
B
C
A
10
3
6
t
V
PHL
90%
50%
10%
DD
14
13
20 ns
11
9
5
4
90%
50%
10%
12
t
THL
8
7
OUT = A+B•C
t
2
1
TLH
t
PLH
20 ns
OUTPUT
V
V
V
V
DD
SS
OH
OL
DD
SS
;
.