CY7C4281-15JC Cypress Semiconductor Corporation., CY7C4281-15JC Datasheet

CY7C4281-15JC

Manufacturer Part Number

CY7C4281-15JC

Description

Manufacturer

Cypress Semiconductor Corporation.

Datasheets

1.CY7C4281-15JC.pdf (16 pages)

2.CY7C4281-15JC.pdf (16 pages)

3.CY7C4281-10JC.pdf (16 pages)

Specifications of CY7C4281-15JC

Package

PLCC

Date_code

05+

Current page: 1 of 16
Download datasheet (344Kb)

Cypress Semiconductor Corporation

Document #: 38-06007 Rev. *C

Features

Logic Block Diagram

• High-speed, low-power, first-in first-out (FIFO)

• 64K × 9 (CY7C4281)

• 128K × 9 (CY7C4291)

• 0.5-micron CMOS for optimum speed/power

• High-speed 100-MHz operation (10-ns read/write cycle

• Low power

• Fully asynchronous and simultaneous read and write

• Empty, Full, and programmable Almost Empty and

• TTL compatible

• Output Enable (OE) pin

• Independent read and write enable pins

• Center power and ground pins for reduced noise

• Supports free-running 50% duty cycle clock inputs

• Width Expansion Capability

• Pin-compatible density upgrade to CY7C42X1

• Pin-compatible density upgrade to

memories

times)

— I

operation

Almost Full status flags

family

IDT72201/11/21/31/41/51

WCLK

= 40 mA

= 2 mA

CONTROL

POINTER

WEN1

WRITE

RESET

LOGIC

WEN2/LD

OUTPUT REGISTER

THREE-STATE

RAMARRAY

128K x 9

Dual Port

64K x 9

INPUT

0–8

•

3901 North First Street

RCLK

PROGRAM

CONTROL

POINTER

FLAG

LOGIC

FLAG

READ

REN1 REN2

64K/128K x 9 Deep Sync FIFOs

Functional Description

The

memories with clocked read and write interfaces. All are nine

bits wide. The CY7C4281/91 are pin-compatible to the

CY7C42X1

features include Almost Full/Almost Empty flags. These FIFOs

provide solutions for a wide variety of data buffering needs,

including high-speed data acquisition, multiprocessor inter-

faces, and communications buffering.

These FIFOs have nine-bit input and output ports that are

controlled by separate clock and enable signals. The input port

is controlled by a free-running clock (WCLK) and two

write-enable pins (WEN1, WEN2/LD).

When WEN1 is LOW and WEN2/LD is HIGH, data is written

into the FIFO on the rising edge of the WCLK signal. While

WEN1, WEN2/LD is held active, data is continually written into

the FIFO on each WCLK cycle. The output port is controlled in

a similar manner by a free-running read clock (RCLK) and two

read

CY7C4281/91 has an output enable pin (OE). The read

(RCLK) and write (WCLK) clocks may be tied together for

single-clock operation or the two clocks may be run indepen-

dently for asynchronous read/write applications. Clock

frequencies up to 100 MHz are achievable. Depth expansion

is possible using one enable input for system control, while the

other enable is controlled by expansion logic to direct the flow

of data.

• Pb-Free Packages Available

PAE

PAF

CY7C4281/91

CY7C4281 CY7C429164K/128K x 9 Deep Sync FIFOs

enable

Pin Configuration

•

REN1

RCLK

REN2

Synchronous

GND

PAE

PAF

San Jose

pins

14 15 16 17 18 19 20

4 3 2 1

(REN1,

are

CY7C4281

CY7C4291

Top View

CA 95134

PLCC

high-speed,

FIFO

REN2).

31 30

Revised August 2, 2005

family.

•

WEN1

WCLK

WEN2/LD

low-power

CY7C4281

CY7C4291

408-943-2600

Programmable

addition,

FIFO

the

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