ISPGAL22V10AB-75LN Lattice Semiconductor Corp., ISPGAL22V10AB-75LN Datasheet

ISPGAL22V10AB-75LN

Manufacturer Part Number

ISPGAL22V10AB-75LN

Description

Manufacturer

Lattice Semiconductor Corp.

Datasheet

1.ISPGAL22V10AV.pdf (16 pages)

Specifications of ISPGAL22V10AB-75LN

Package

QFN32

Date_code

05+

Current page: 1 of 16
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brand or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without

notice.

www.latticesemi.com

January 2004

Features

High Performance

Low Power

Space-Saving Packaging

Easy System Integration

In-System Programmable

Applications Include

Boundary Scan USERCODE Register

• t

• f

• t

• 1.8V core E

• Typical standby power <300µW

• CMOS design techniques provide low static and

• Available in 32-pin QFN (Quad Flat-pack No

• Operation with 3.3V (ispGAL22V10AV), 2.5V

• Operation with 3.3V, 2.5V or 1.8V LVCMOS I/O

• 5V tolerant I/O for LVCMOS 3.3 interface

• Hot-socketing

• Open-drain capability

• Input pull-up, pull-down or bus-keeper

• Lead-free package option

• Programmable output slew rate

• 3.3V PCI compatible

• IEEE 1149.1 boundary scan testable

• 3.3V/2.5V/1.8V in-system programmable

• In-system programmable logic

• 100% tested/100% yields

• High speed electrical erasure (<50ms)

• DMA control

• State machine control

• High speed graphics processing

• Software-driven hardware conﬁguration

• Supports electronic signature

output

(ispGAL22V10AC)

dynamic power

lead), 5mm x 5mm body size

(ispGAL22V10AB) or 1.8V (ispGAL22V10AC)

supplies

(ISP™) using IEEE 1532 compliant interface

CELL TECHNOLOGY

MAX

= 1.3 ns clock set-up time

= 2.3ns propagation delay

= 2ns maximum from clock input to data

= 455 MHz maximum operating frequency

CMOS

technology

Introduction

The ispGAL22V10A is manufactured using Lattice

Semiconductor’s advanced E

combines CMOS with Electrically Erasable (E

gate technology. With an advanced E

and full CMOS logic approach, the ispGAL22V10A fam-

ily offers fast pin-to-pin speeds, while simultaneously

delivering low standby power without requiring any

“turbo bits” or other traditional power management

schemes. The ispGAL22V10A can interface with both

3.3V, 2.5V and 1.8V signal levels.

The ispGAL22V10A is functionally compatible with the

ispGAL22LV10, GAL22LV10 and GAL22V10.

Figure 1. Functional Block Diagram

ispGAL22V10AV/B/C

TDO

TMS

TCK

TDI

I/CLK

PROGRAMMING

In-System Programmable Low Voltage

LOGIC

CMOS PLD Generic Array Logic

´®

CMOS process, which

PRESET

RESET

OLMC

low-power cell

isp22v10a_02

Data Sheet

) ﬂoating

I/O

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