ADSP21062LKS-160 Analog Devices, ADSP21062LKS-160 Datasheet
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ADSP21062LKS-160
Manufacturer Part Number
ADSP21062LKS-160
Description
Manufacturer
Analog Devices
Datasheet
1.ADSP21062CS160.pdf
(48 pages)
Specifications of ADSP21062LKS-160
Package
QFP240
Date_code
09+
a
SHARC is a registered trademark of Analog Devices, Inc.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
SUMMARY
High Performance Signal Processor for Communica-
Super Harvard Architecture
32-Bit IEEE Floating-Point Computation Units—
Dual-Ported On-Chip SRAM and Integrated I/O
Integrated Multiprocessing Features
KEY FEATURES
40 MIPS, 25 ns Instruction Rate, Single-Cycle Instruction
120 MFLOPS Peak, 80 MFLOPS Sustained Performance
Dual Data Address Generators with Modulo and Bit-
Efficient Program Sequencing with Zero-Overhead
tions, Graphics and Imaging Applications
Four Independent Buses for Dual Data Fetch,
Instruction Fetch and Nonintrusive I/O
Multiplier, ALU, and Shifter
Peripherals—A Complete System-On-A-Chip
Execution
Reverse Addressing
Looping: Single-Cycle Loop Setup
MULTIPLIER
8 x 4 x 32
DAG1
CONNECT
BUS
(PX)
8 x 4 x 24
DAG2
CORE PROCESSOR
REGISTER
16 x 40-BIT
DATA
FILE
PM ADDRESS BUS
DM ADDRESS BUS
TIMER
PM DATA BUS
DM DATA BUS
BARREL
SHIFTER
SEQUENCER
PROGRAM
Figure 1. ADSP-21062/ADSP-21062L Block Diagram
INSTRUCTION
32 x 48-BIT
CACHE
48
40/32
32
24
ALU
ADDR
PROCESSOR PORT
ADDR
DUAL-PORTED SRAM
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
DUAL-PORTED BLOCKS
DATA
TWO INDEPENDENT
IEEE JTAG Standard 1149.1 Test Access Port and
240-Lead Thermally Enhanced MQFP Package
225-Ball Plastic Ball Grid Array (PBGA)
32-Bit Single-Precision and 40-Bit Extended-Precision
Parallel Computations
Single-Cycle Multiply and ALU Operations in Parallel with
Multiply with Add and Subtract for Accelerated FFT
2 Mbit On-Chip SRAM
Dual-Ported for Independent Access by Core Processor
Off-Chip Memory Interfacing
4 Gigawords Addressable
Programmable Wait State Generation, Page-Mode
On-Chip Emulation
IEEE Floating-Point Data Formats or 32-Bit Fixed-
Point Data Format
Dual Memory Read/Writes and Instruction Fetch
Butterfly Computation
and DMA
DRAM Support
ADSP-21062/ADSP-21062L
(
DATA BUFFERS
MEMORY MAPPED)
DATA
REGISTERS
CONTROL,
STATUS &
DSP Microcomputer Family
IOP
DATA
I/O PROCESSOR
I/O PORT
DATA
IOD
48
ADDR
ADSP-2106x SHARC
SERIAL PORTS
CONTROLLER
World Wide Web Site: http://www.analog.com
ADDR
LINK PORTS
IOA
17
DMA
(2)
(6)
MULTIPROCESSOR
EXTERNAL
INTERFACE
DATA BUS
ADDR BUS
HOST PORT
36
© Analog Devices, Inc., 1999
6
6
PORT
MUX
4
EMULATION
MUX
JTAG
TEST &
32
48
7
®