MC100EP105MNG ON Semiconductor, MC100EP105MNG Datasheet - Page 2
![no-image](/images/manufacturer_photos/0/4/495/on_semiconductor_sml.jpg)
MC100EP105MNG
Manufacturer Part Number
MC100EP105MNG
Description
IC GATE AND/NAND QUAD 2INP 32QFN
Manufacturer
ON Semiconductor
Series
100EPr
Datasheet
1.MC10EP105FAR2.pdf
(11 pages)
Specifications of MC100EP105MNG
Logic Type
AND/NAND Gate
Number Of Circuits
4
Number Of Inputs
8 Input (2, 2, 2, 2)
Schmitt Trigger Input
No
Output Type
Differential
Voltage - Supply
3 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-TFQFN Exposed Pad
Product
MUX Gates
Logic Family
MC100EP
High Level Output Current
- 50 mA
Low Level Output Current
50 mA
Propagation Delay Time
0.35 ns
Supply Voltage (max)
+/- 5.5 V
Supply Voltage (min)
+/- 3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Output High, Low
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC100EP105MNG
Manufacturer:
ON Semiconductor
Quantity:
135
Company:
Part Number:
MC100EP105MNG
Manufacturer:
ON Semiconductor
Quantity:
4
D0b
D0a
D0a
V
V
V
Q0
Q0
CC
CC
EE
Warning: All V
to Power Supply to guarantee proper operation.
D0a
D0a
D0b
D0b
D1a
D1a
D1b
D1b
D2a
D2a
D2b
D2b
D3a
D3a
D3b
D3b
V
EE
Figure 1. 32−Lead LQFP Pinout (Top View)
25
26
27
28
29
30
31
32
D0b D1a
V
24
1
CC
CC
Q1
Figure 3. Logic Diagram
23
2
and V
D1a
Q1
22
3
MC100EP105
MC10EP105
EE
D1b
Q2
21
4
pins must be externally connected
D1b
Q2
20
5
D2a
Q3
19
6
D2a
Q3
18
7
D2b
V
17
8
CC
http://onsemi.com
16
15
14
13
12
11
10
Q0
Q0
Q1
Q1
Q2
Q3
Q3
9
Q2
2
D2b
D3a
D3a
V
D3b
D3b
V
NC
CC
EE
D0b
D0a
D0a
V
V
V
Table 2. TRUTH TABLE
Q0
Q0
* Pins will default LOW when left open.
CC
CC
EE
Table 1. PIN DESCRIPTION
Qn, Qn
V
V
Dna*, Dnb*, Dna*, Dnb*
NC
PIN
Dna
CC
EE
L
L
H
H
25
26
27
28
29
30
31
32
Figure 2. 32−Lead QFN Pinout (Top View)
D0b D1a
V
24
CC
1
Dnb
L
H
L
H
Q1
23
2
D1a
Q1
Dna
22
3
H
H
L
L
Exposed Pad (EP)
D1b
Q2
21
4
Dnb
H
L
H
L
D1b
ECL Data Inputs
ECL Data Outputs
Positive Supply
Negative Supply
No Connect
Q2
20
FUNCTION
5
D2a
Q3
19
6
Qn
L
L
L
H
D2a
Q3
18
7
D2b
V
17
Qn
CC
8
H
H
H
L
16
15
14
13
12
10
11
9
D2b
D3a
D3a
V
D3b
D3b
V
NC
CC
EE