MC14042B
Quad Transparent Latch
P−channel and N−channel enhancement mode devices in a single
monolithic structure. Each latch has a separate data input, but all four
latches share a common clock. The clock polarity (high or low) used to
strobe data through the latches can be reversed using the polarity
input. Information present at the data input is transferred to outputs Q
and Q during the clock level which is determined by the polarity input.
When the polarity input is in the logic “0” state, data is transferred
during the low clock level, and when the polarity input is in the logic
“1” state the transfer occurs during the high clock level.
Features
•
•
•
•
•
•
•
•
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Temperature Derating:
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
to the range V
(e.g., either V
*For additional information on our Pb−Free strategy and soldering details, please
MAXIMUM RATINGS
© Semiconductor Components Industries, LLC, 2005
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Symbol
V
I
The MC14042B Quad Transparent Latch is constructed with MOS
This device contains protection circuitry to guard against damage due to high
Unused inputs must always be tied to an appropriate logic voltage level
Schottky TTL Load Over the Rated Temperature Range
Buffered Data Inputs
Common Clock
Clock Polarity Control
Q and Q Outputs
Double Diode Input Protection
Supply Voltage Range = 3.0 Vdc to 1 8 Vdc
Capable of Driving Two Low−power TTL Loads or One Low−power
Pb−Free Packages are Available*
in
in
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
V
T
P
, V
, I
T
T
DD
stg
D
A
L
out
out
DC Supply Voltage Range
Input or Output Voltage Range
Input or Output Current
Power Dissipation,
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
SS
SS
(DC or Transient)
(DC or Transient) per Pin
per Package (Note 1)
(8−Second Soldering)
or V
v (V
DD
in
). Unused outputs must be left open.
Parameter
or V
(Voltages Referenced to V
out
) v V
DD
.
in
and V
−0.5 to V
−0.5 to +18.0
SS
−55 to +125
−65 to +150
out
)
Value
± 10
500
260
should be constrained
DD
+ 0.5
1
Unit
mW
mA
°C
°C
°C
V
V
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
A
WL, L
YY, Y
WW, W
G
CASE 751B
SOEIAJ−16
CASE 648
CASE 966
P SUFFIX
D SUFFIX
F SUFFIX
PDIP−16
SOIC−16
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator
Publication Order Number:
16
1
16
16
1
1
DIAGRAMS
MARKING
MC14042BCP
AWLYYWWG
MC14042B
AWLYWW
MC14042B/D
14042BG
ALYWG