74ACT573SC Fairchild Semiconductor, 74ACT573SC Datasheet - Page 2

• Manufacturer Part Number: 74ACT573SC
• Description: IC LATCH OCTAL 3 STATE 20-SOIC
• Manufacturer: Fairchild Semiconductor
• Series: 74ACTr
• Type: D-Typer

Specifications of 74ACT573SC

• Logic Type: D-Type Transparent Latch
• Circuit: 8:8
• Output Type: Tri-State
• Voltage - Supply: 4.5 V ~ 5.5 V
• Independent Circuits: 1
• Delay Time - Propagation: 6ns
• Current - Output High, Low: 24mA, 24mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Number Of Circuits: 8
• Logic Family: 74ACT
• Polarity: Non-Inverting
• Input Bias Current (max): 4 uA
• High Level Output Current: - 24 mA
• Low Level Output Current: 24 mA
• Propagation Delay Time: 10.5 ns at 5 V
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Bits: 8
• Number Of Elements: 1
• Latch Mode: Transparent
• Technology: CMOS
• Package Type: SOIC W
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

©1988 Fairchild Semiconductor Corporation
74AC573, 74ACT573 Rev. 1.6.0
Connection Diagram
Pin Description
Functional Description
The 74AC573 and 74ACT573 contain eight D-type
latches with 3-STATE output buffers. When the Latch
Enable (LE) input is HIGH, data on the D
the latches. In this condition the latches are transparent,
i.e., a latch output will change state each time its D-type
input changes. When LE is LOW the latches store the
information that was present on the D-type inputs a
setup time preceding the HIGH-to-LOW transition of LE.
The 3-STATE buffers are controlled by the Output
Enable (OE) input. When OE is LOW, the buffers are
enabled. When OE is HIGH the buffers are in the high
impedance mode but this does not interfere with entering
new data into the latches.
D
LE
OE
O
0
0
Pin Names
–D
–O
7
7
Data Inputs
Latch Enable Input
3-STATE Output Enable Input
3-STATE Latch Outputs
Description
n
inputs enters
2
Logic Symbols
Truth Table
H
L
Z
X
O
Latch Enable
0
LOW Voltage
High Impedance
OE
Immaterial
HIGH Voltage
H
L
L
L
Previous O
Inputs
LE
0
H
H
X
L
before HIGH-to-LOW transition of
IEEE/IEC
D
H
X
X
L
Outputs
www.fairchildsemi.com
O
O
H
L
Z
n
0