DS34LV86TM+ National Semiconductor, DS34LV86TM+ Datasheet

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DS34LV86TM+

Manufacturer Part Number
DS34LV86TM+
Description
Manufacturer
National Semiconductor
Datasheet

Specifications of DS34LV86TM+

Notes
NEW
Date_code
10+
© 2002 National Semiconductor Corporation
DS34LV86T
3V Enhanced CMOS Quad Differential Line Receiver
General Description
The DS34LV86T is a high speed quad differential CMOS
receiver that meets the requirements of both TIA/EIA-422-B
and ITU-T V.11. The CMOS DS34LV86T features typical low
static I
and power conscious applications. The TRI-STATE
ables, EN, allow the device to be disabled when not in use to
minimize power consumption. The dual enable scheme al-
lows for flexibility in turning receivers on and off.
The receiver output (RO) is guaranteed to be High when the
inputs are left open. The receiver can detect signals as low
as
receiver outputs (RO) are compatible with TTL and LVCMOS
levels.
Connection Diagram
TRI-STATE
±
200 mV over the common mode range of
CC
®
is a registered trademark of National Semiconductor Corporation.
of 9 mA which makes it ideal for battery powered
See NS Package Number M16A
Order Number DS34LV86TM
Dual-In-Line Package
Top View
DS012644
01264401
±
10V. The
®
en-
Features
n Low power CMOS design (30 mW typical)
n Interoperable with existing 5V RS-422 networks
n Industrial temperature range
n Meets TIA/EIA-422-B (RS-422) and ITU-T V.11
n 3.3V Operation
n
n
n Receiver OPEN input failsafe feature
n Guaranteed AC parameter:
n Pin compatible with DS34C86T
n 32 MHz Toggle Frequency
n
n Available in SOIC packaging
Truth Table
L = Logic Low
H = Logic High
X = Irrelevant
Z = TRI-STATE
= Open, Not Terminated
recommendation
±
±
>
7V common mode range
10V common mode range
6.5k ESD Tolerance (HBM)
Maximum Receiver Skew: 4 ns
Transition time: 10 ns
Enable
EN
H
H
H
L
V
V
ID
ID
RI+–RI−
Inputs
Open
X
@
+0.2V
−0.2V
@
V
V
ID
ID
= 3V
= 0.2V
www.national.com
Output
March 2002
RO
H
H
Z
L

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