CY7C026A-12AC Cypress Semiconductor Corporation., CY7C026A-12AC Datasheet

CY7C026A-12AC

Manufacturer Part Number

CY7C026A-12AC

Description

Manufacturer

Cypress Semiconductor Corporation.

Datasheets

1.CY7C026A-12AC.pdf (18 pages)

2.CY7C026A-12AC.pdf (17 pages)

3.CY7C026A-12AC.pdf (17 pages)

Specifications of CY7C026A-12AC

Case

TQFP

Date_code

Current page: 1 of 18
Download datasheet (500Kb)

Cypress Semiconductor Corporation

Document #: 38-06046 Rev. *C

Features

Notes:

CY7C026A

CY7C036A16K x 16/18 Dual-Port Static RAM

1. See page 6 for Load Conditions.

2. I/O

3. I/O

4. BUSY is an output in master mode and an input in slave mode.

• True dual-ported memory cells that allow simultaneous

• 16K x 16 organization (CY7C026A)

• 16K x 18 organization (CY7C036A)

• 0.35-micron CMOS for optimum speed/power

• High-speed access: 12

• Low operating power

• Fully asynchronous operation

• Automatic power-down

Logic Block Diagram

R/W

I/O

R/W

SEM

BUSY

INT

access of the same memory location

— Active: I

— Standby: I

8/9L

–A

–I/O

13L

–I/O

[4]

for x16 devices; I/O

[3]

for x16 devices; I/O

7/8L

[2]

15/17L

SB3

= 180 mA (typical)

= 0.05 mA (typical)

8/9

–I/O

[1]

–I/O

/15/20 ns

for x18 devices.

Address

Decode

for x18 devices.

•

198 Champion Court

Control

I/O

True Dual-Ported

Semaphore

RAM Array

Arbitration

Interrupt

16K x 16/18 Dual-Port Static RAM

M/S

• Expandable data bus to 32/36 bits or more using

• On-chip arbitration logic

• Semaphores included to permit software handshaking

• INT flags for port-to-port communication

• Separate upper-byte and lower-byte control

• Pin select for Master or Slave

• Commercial and Industrial temperature ranges

• Available in 100-Pin TQFP

• Pb-Free packages available

Master/Slave chip select when using more than one

device

between ports

Control

I/O

•

San Jose

Address

Decode

CA 95134-1709

Revised September 6, 2005

8/9

I/O

•

CY7C026A

CY7C036A

8/9L

I/O

408-943-2600

[4]

–I/O

BUSY

SEM

R/W

–A

15/17R

R/W

[2]

INT

[3]

7/8R

13R

[+] Feedback

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