CY7C4255-15AI Cypress Semiconductor Corporation., CY7C4255-15AI Datasheet

CY7C4255-15AI

Manufacturer Part Number

CY7C4255-15AI

Description

Manufacturer

Cypress Semiconductor Corporation.

Datasheet

1.CY7C4255-15AI.pdf (20 pages)

Specifications of CY7C4255-15AI

Case

QFP

Date_code

04+

Current page: 1 of 20
Download datasheet (422Kb)

Features

Functional Description

The CY7C4255/65 are high-speed, low-power, first-in first-out

(FIFO) memories with clocked read and write interfaces. All

Cypress Semiconductor Corporation

• High-speed, low-power, first-in first-out (FIFO)

• 8K x 18 (CY7C4255)

• 16K x 18 (CY7C4265)

• 0.5 micron CMOS for optimum speed/power

• High-speed 100-MHz operation (10 ns read/write cycle

• Low power — I

• Fully asynchronous and simultaneous read and write

• Empty, Full, Half Full, and programmable Almost Empty

• TTL compatible

• Retransmit function

• Output Enable (OE) pins

• Independent read and write enable pins

• Center power and ground pins for reduced noise

• Supports free-running 50% duty cycle clock inputs

• Width Expansion Capability

• Depth Expansion Capability

• 64-pin PLCC and 64-pin TQFP

• Pin-compatible density upgrade to CY7C42X5 family

• Pin-compatible density upgrade to

Logic Block Diagram

memories

times)

operation

and Almost Full status flags

IDT72205/15/25/35/45

WXO/HF

=45 mA

FL/RT

RXO

WXI

RXI

WCLK

EXPANSION

CONTROL

POINTER

RESET

WRITE

LOGIC

WEN

•

3901 North First Street

PRELIMINARY

OUTPUT REGISTER

THREE–STATE

16K x 18

8K x 18

ARRAY

INPUT

RAM

0 – 17

are 18 bits wide and are pin/functionally compatible to the

CY7C42X5 Synchronous FIFO family. The CY7C4255/65 can

be cascaded to increase FIFO depth. Programmable features

include Almost Full/Almost Empty flags. These FIFOs provide

solutions for a wide variety of data buffering needs, including

high-speed data acquisition, multiprocessor interfaces, and commu-

nications buffering.

These FIFOs have 18-bit input and output ports that are con-

trolled by separate clock and enable signals. The input port is

controlled by a free-running clock (WCLK) and a write enable

pin (WEN).

When WEN is asserted, data is written into the FIFO on the rising

edge of the WCLK signal. While WEN is held active, data is continu-

ally written into the FIFO on each cycle. The output port is controlled

in a similar manner by a free-running read clock (RCLK) and a read

enable pin (REN). In addition, the CY7C4255/65 have an output

enable pin (OE). The read and write clocks may be tied together for

single-clock operation or the two clocks may be run independently for

asynchronous read/write applications. Clock frequencies up to 100

MHz are achievable.

Retransmit and Synchronous Almost Full/Almost Empty flag

features are available on these devices.

Depth expansion is possible using the cascade input (WXI,

RXI), cascade output (WXO, RXO), and First Load (FL) pins. The

WXO and RXO pins are connected to the WXI and RXI pins of the

next device, and the WXO and RXO pins of the last device should be

connected to the WXI and RXI pins of the first device. The FL pin of

the first device is tied to V

es should be tied to V

8K/16Kx18 Deep Sync FIFOs

•

RCLK

San Jose

PROGRAM

CONTROL

POINTER

FLAG

LOGIC

READ

FLAG

REN

July 1995 – Revised November 1996

4255–1

•

and the FL pin of all the remaining devic-

PAE

PAF

SMODE

CA 95134

CY7C4255

CY7C4265

•

fax id: 5413

408-943-2600

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