IDT74ALVCH16260PAG IDT, Integrated Device Technology Inc, IDT74ALVCH16260PAG Datasheet - Page 3

• Manufacturer Part Number: IDT74ALVCH16260PAG
• Description: IC LATCH 12-24BIT 3.3V 56-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 74ALVCHr
• Type: D-Typer

Specifications of IDT74ALVCH16260PAG

• Logic Type: D-Type Transparent Latch
• Circuit: 12:24
• Output Type: Tri-State
• Voltage - Supply: 2.3 V ~ 3.6 V
• Independent Circuits: 1
• Delay Time - Propagation: 1ns
• Current - Output High, Low: 24mA, 24mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Logic Family: ALVC
• Number Of Bits: 12
• Number Of Elements: 1
• Latch Mode: Multiplexed
• Polarity: Non-Inverting
• Technology: CMOS
• Package Type: TSSOP
• Propagation Delay Time: 6.9ns
• Operating Supply Voltage (typ): 3.3V
• High Level Output Current: -24mA
• Low Level Output Current: 24mA
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74ALVCH16260PAG

FUNCTION TABLES
NOTES:
1. H = HIGH Voltage Level
2. Output level before the indicated steady-state input conditions were established.
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
PIN DESCRIPTION
IDT74ALVCH16260
3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
Pin Names
Ax
H
H
H
X
X
X
X
X
L
L
L
1
2
Ax
LEA1B
LEA2B
Bx
Bx
OE1B
OE2B
LE1B
LE2B
OEA
SEL
(1:12)
(1:12)
(1:12)
LEA1B
H
H
H
H
L
L
L
X
X
X
X
I/O
I/O
I/O
I/O
I
I
I
I
I
I
LEA2B
I
I
H
H
H
H
L
L
L
X
X
X
X
Inputs
A-TO-B (OEA = H)
Bidirectional Data Port A. Usually connected to the CPU's address/data bus.
Bidirectional Data Port 1B. Usually connected to the even path or even bank of memory.
Bidirectional Data Port 2B. Usually connected to the odd path or odd bank of memory.
Latch Enable Input for A-1B Latch. The latch is open when LEA1B is HIGH. Data from the A-port is latched on the HIGH to LOW
transition of LEA1B.
Latch Enable Input for A-2B Latch. The latch is open when LEA2B is HIGH. Data from the A-port is latched on the HIGH to LOW
transition of LEA2B.
Latch Enable Input for 1B-A Latch. The latch is open when LE1B is HIGH. Data from the A-port is latched on the HIGH to LOW
transition of LE1B.
Latch Enable Input for 2B-A Latch. The latch is open when LE2B is HIGH. Data from the A-port is latched on the HIGH to LOW
transition of LE2B.
1B or 2B Port Selection. When HIGH, SEL enables data transfer from 1B Port to A Port. When LOW, SEL enables data transfer from
2B Port to A Port.
Output Enable for A Port (Active LOW)
Output Enable for 1B Port (Active LOW)
Output Enable for 2B Port (Active LOW)
OE1B
H
H
L
L
L
L
L
L
L
L
L
(CONTINUED)
OE2B
H
H
L
L
L
L
L
L
L
L
L
Active
Active
1B
1B
1B
(1)
1Bx
H
H
L
L
Z
Z
0
0
0
(2)
(2)
(2)
Outputs
Active
Active
2B
2B
2B
2Bx
H
H
L
L
Z
Z
0
0
0
(2)
(2)
(2)
3
Description
(1)
(1)
(1)
INDUSTRIAL TEMPERATURE RANGE