MC74HC573ADTR2G ON Semiconductor, MC74HC573ADTR2G Datasheet - Page 2

• Manufacturer Part Number: MC74HC573ADTR2G
• Description: IC LATCH TRANSP OCTAL 20-TSSOP
• Manufacturer: ON Semiconductor
• Series: 74HCr

Specifications of MC74HC573ADTR2G

• Logic Type: D-Type Transparent Latch
• Circuit: 8:8
• Output Type: Tri-State
• Voltage - Supply: 2 V ~ 6 V
• Independent Circuits: 1
• Delay Time - Propagation: 26ns
• Current - Output High, Low: 7.8mA, 7.8mA
• Operating Temperature: -55°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Number Of Circuits: 8
• Logic Family: 74HC
• Polarity: Non-Inverting
• Input Bias Current (max): 4 uA
• High Level Output Current: - 7.8 mA
• Low Level Output Current: 32 mA
• Propagation Delay Time: 150 ns at 2 V, 100 ns at 3 V, 30 ns at 4.5 V, 26 ns at 6 V
• Supply Voltage (max): 6 V
• Supply Voltage (min): 2 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 55 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
*This package is inherently Pb−Free.
ORDERING INFORMATION
Specifications Brochure, BRD8011/D.
MC74HC573AN
MC74HC573ANG
MC74HC573ADW
MC74HC573ADWG
MC74HC573ADWR2
MC74HC573ADWR2G
MC74HC573ADT
MC74HC573ADTG
MC74HC573ADTR2
MC74HC573ADTR2G
MC74HC573AFEL
MC74HC573AFELG
X = Don’t Care
Z = High Impedance
Output
Enable
OUTPUT
ENABLE
H
L
L
L
GND
Device
D0
D2
D3
D1
D4
D5
D6
D7
FUNCTION TABLE
PIN ASSIGNMENT
Enable
Inputs
Latch
H
H
X
1
2
3
4
5
6
7
8
9
10
L
D
H
X
X
L
20
19
18
17
16
15
14
13
12
11
No Change
V
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
LATCH
ENABLE
Output
CC
Q
H
Z
L
http://onsemi.com
SOIC−20 WIDE
SOIC−20 WIDE
SOIC−20 WIDE
SOIC−20 WIDE
OUTPUT ENABLE
TSSOP−20*
TSSOP−20*
TSSOP−20*
TSSOP−20*
SOEIAJ−20
SOEIAJ−20
(Pb−Free)
(Pb−Free)
(Pb−Free)
(Pb−Free)
INPUTS
LATCH ENABLE
Package
SOIC−20
PDIP−20
*Equivalent to a two−input NAND gate.
Internal Gate Count*
Internal Gate Progation Delay
Internal Gate Power Dissipation
Speed Power Product
DATA
2
D0
D1
D2
D3
D4
D5
D6
D7
Design Criteria
2
3
4
5
6
7
8
9
11
1
LOGIC DIAGRAM
PIN 20 = V
PIN 10 = GND
19
18
17
16
15
14
13
12
1000 Tape & Reel
1000 Tape & Reel
2500 Tape & Reel
2500 Tape & Reel
2000 Tape & Reel
2000 Tape & Reel
18 Units / Rail
18 Units / Rail
38 Units / Rail
38 Units / Rail
75 Units / Rail
75 Units / Rail
0.0075
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Value
54.5
Shipping
1.5
5.0
CC
NONINVERTING
OUTPUTS
Units
†
mW
ea.
ns
pJ