MC74HCT573ADWR2G ON Semiconductor, MC74HCT573ADWR2G Datasheet

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MC74HCT573ADWR2G

Manufacturer Part Number
MC74HCT573ADWR2G
Description
IC LATCH OCTAL 3ST LSTTL 20SOIC
Manufacturer
ON Semiconductor
Series
74HCTr
Type
D-Typer
Datasheet

Specifications of MC74HCT573ADWR2G

Logic Type
D-Type Transparent Latch
Circuit
8:8
Output Type
Tri-State
Voltage - Supply
4.5 V ~ 5.5 V
Independent Circuits
1
Delay Time - Propagation
30ns
Current - Output High, Low
6mA, 6mA
Operating Temperature
-55°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
20-SOIC (7.5mm Width)
Logic Family
HCT
Number Of Bits
8
Number Of Elements
1
Latch Mode
Transparent
Polarity
Non-Inverting
Technology
CMOS
Package Type
SOIC W
Propagation Delay Time
45ns
Operating Supply Voltage (typ)
5V
High Level Output Current
-6mA
Low Level Output Current
6mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
-55C to 125C
Operating Temperature Classification
Military
Mounting
Surface Mount
Pin Count
20
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
MC74HCT573ADWR2GOS

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC74HCT573ADWR2G
Manufacturer:
ON Semiconductor
Quantity:
500
Part Number:
MC74HCT573ADWR2G
Manufacturer:
ON
Quantity:
20 000
MC74HCT573A
Octal 3−State Noninverting
Transparent Latch with
LSTTL Compatible Inputs
High−Performance Silicon−Gate CMOS
device may be used as a level converter for interfacing TTL or NMOS
outputs to High−Speed CMOS inputs.
asynchronously) when Latch Enable is high. When Latch Enable goes
low, data meeting the setup and hold times becomes latched.
when Output Enable is high, all device outputs are forced to the
high−impedance state. Thus, data may be latched even when the
outputs are not enabled.
Data Inputs on the opposite side of the package from the outputs to
facilitate PC board layout.
w
© Semiconductor Components Industries, LLC, 2006
March, 2006 − Rev. 11
The MC74HCT573A is identical in pinout to the LS573. This
These latches appear transparent to data (i.e., the outputs change
The Output Enable input does not affect the state of the latches, but
The HCT573A is identical in function to the HCT373A but has the
No. 7A
These devices are available in Pb−free package(s). Specifications herein
apply to both standard and Pb−free devices. Please see our website at
www.onsemi.com for specific Pb−free orderable part numbers, or
contact your local ON Semiconductor sales office or representative.
Output Drive Capability: 15 LSTTL Loads
TTL/NMOS−Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 10 μA
In Compliance with the Requirements Defined by JEDEC Standard
Chip Complexity: 234 FETs or 58.5 Equivalent Gates
— Improved Propagation Delays
— 50% Lower Quiescent Power
1
20
MC74HCT573AN
MC74HCT573ADW
MC74HCT573ADWR2 SOIC−WIDE
MC74HCT573ADT
MC74HCT573ADTR2
20
20
1
1
Device
1
ORDERING INFORMATION
A
WL = Wafer Lot
YY = Year
WW = Work Week
SOIC WIDE−20
http://onsemi.com
DW SUFFIX
CASE 751D
= Assembly Location
CASE 948E
TSSOP−20
DT SUFFIX
CASE 738
N SUFFIX
PDIP−20
SOIC−WIDE
Publication Order Number:
TSSOP−20
TSSOP−20
Package
PDIP−20
MC74HCT573A/D
20
1
20
MC74HCT573AN
1
DIAGRAMS
MARKING
AWLYYWW
AWLYYWW
20
HCT573A
1
1000 / Reel
2500 / Reel
1440 / Box
Shipping
38 / Rail
75 / Rail
ALYW
573A
HCT

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MC74HCT573ADWR2G Summary of contents

Page 1

... These devices are available in Pb−free package(s). Specifications herein apply to both standard and Pb−free devices. Please see our website at www.onsemi.com for specific Pb−free orderable part numbers, or contact your local ON Semiconductor sales office or representative. © Semiconductor Components Industries, LLC, 2006 March, 2006 − Rev. 11 http://onsemi.com PDIP− ...

Page 2

LOGIC DIAGRAM DATA INPUTS LATCH ENABLE PIN OUTPUT ENABLE PIN 10 ...

Page 3

... Current Î Î Î Î Î Î Î Î Î Î Î Î Î Î NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). Î Î Î Î Î Î Î Î ...

Page 4

... PD * Used to determine the no−load dynamic power consumption Semiconductor High−Speed CMOS Data Book (DL129/D). TIMING REQUIREMENTS Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ...

Page 5

V INPUT D 1 PLH 90% 1 10% t TLH Figure 1. OUTPUT ENABLE 1 PZL PLZ Q 1 PZH PHZ Q 1.3 V Figure ...

Page 6

SEATING PLANE 20X 0. 18X PACKAGE DIMENSIONS PDIP−20 N SUFFIX PLASTIC DIP PACKAGE CASE 738−03 ISSUE ...

Page 7

... N F DETAIL DETAIL E N. American Technical Support: 800−282−9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 http://onsemi.com 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. ...

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