CY7C148-45DMB Cypress Semiconductor Corporation., CY7C148-45DMB Datasheet

CY7C148-45DMB

Manufacturer Part Number

CY7C148-45DMB

Description

Manufacturer

Cypress Semiconductor Corporation.

Datasheet

1.CY7C148-45DMB.pdf (9 pages)

Specifications of CY7C148-45DMB

Date_code

00+

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Company:

Bonase Electronics (HK) Co., Limited

Part Number:

CY7C148-45DMB

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Cypress Semiconductor Corporation

Document #: 38-05059 Rev. **

Features

Functional Description

The CY7C148 and CY7C149 are high-performance CMOS

static RAMs organized as 1024 by 4 bits. Easy memory expan-

Selection Guide

• Automatic power-down when deselected (7C148)

• CMOS for optimum speed/power

• 25-ns access time

• Low active power

• Low standby power (7C148)

• 5-volt power supply 10% tolerance, both commercial

• TTL-compatible inputs and outputs

Maximum Access Time (ns)

Maximum Operating

Current (mA)

Maximum Standby

Current (mA)

Logic Block Diagram

and military

— 440 mW (commercial)

— 605 mW (military)

— 82.5 mW (25-ns version)

— 55 mW (all others)

INPUTBUFFER

DECODER

Commercial

Military

Commercial

Military

COLUMN

64 x 64

ARRAY

POWER

(7C148)

DOWN

•

7C148 25

3901 North First Street

7C148 35

110

C148–1

I/O

sion is provided by an active LOW chip select (CS) input and

three-state outputs. The CY7C148 remains in a low-power

mode as long as the device remains unselected; i.e., (CS) is

HIGH, thus reducing the average power requirements of the

device. The chip select (CS) of the CY7C149 does not affect

the power dissipation of the device.

Writing to the device is accomplished when the chip select

(CS) and write enable (WE) inputs are both LOW. Data on the

I/O pins (I/O

tions specified on the address pins (A

Reading the device is accomplished by taking chip select (CS)

LOW while write enable (WE) remains HIGH. Under these

conditions, the contents of the location specified on the

address pins will appear on the four data I/O pins.

The I/O pins remain in a high-impedance state when chip se-

lect (CS) is HIGH or write enable (WE) is LOW.

Pin Configurations

7C148 45

•

110

San Jose

GND

through I/O

A 6

A 5

A 4

A 3

A 0

A 1

A 2

A 13

A 10

A 11

A 12

A 4

7C149 25

Top View

2 1

8 9

DIP

LCC

•

1011

1817

) is written into the memory loca-

1Kx4 Static RAM

CA 95134

I/O 1

A 8

A 9

I/O 0

I/O 2

Revised September 18, 2001

C148–3

C148–2

V CC

A 7

A 8

A 9

I/O 0

I/O 1

I/O 2

I/O 3

7C149 35

110

through A

•

CY7C148

CY7C149

408-943-2600

7C149 45

110

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