74ALVC16841MTD Fairchild Semiconductor, 74ALVC16841MTD Datasheet

74ALVC16841MTD

Manufacturer Part Number

74ALVC16841MTD

Description

IC LATCH TRANSP 20BIT LV 56TSSOP

Manufacturer

Fairchild Semiconductor

Series

74ALVCr

Datasheet

1.74ALVC16841MTD.pdf (6 pages)

Specifications of 74ALVC16841MTD

Logic Type

D-Type Transparent Latch

Circuit

10:10

Output Type

Tri-State

Voltage - Supply

1.65 V ~ 3.6 V

Independent Circuits

Delay Time - Propagation

1ns

Current - Output High, Low

24mA, 24mA

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

56-TSSOP

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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74ALVC16841MTD

74ALVC16841

Low Voltage 20-Bit Transparent Latch

with 3.6V Tolerant Inputs and Outputs

General Description

The ALVC16841 contains twenty non-inverting latches with

3-STATE outputs and is intended for bus oriented applica-

tions. The device is byte controlled. The flip-flops appear

transparent to the data when the Latch enable (LE) is

HIGH. When LE is LOW, the data that meets the setup time

is latched. Data appears on the bus when the Output

Enable (OE) is LOW. When OE is HIGH, the outputs are in

a high impedance state.

The 74ALVC16841 is designed for low voltage (1.65V to

3.6V) V

The 74ALVC16841 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing low CMOS power dissipation.

Ordering Code:

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

Order Number

applications with I/O compatibility up to 3.6V.

Package Number

MTD56

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

DS500690

Features

I 1.65V–3.6V V

I 3.6V tolerant inputs and outputs

I t

I Power-off high impedance inputs and outputs

I Supports live insertion and withdrawal (Note 1)

I Uses patented noise/EMI reduction circuitry

I Latchup conforms to JEDEC JED78

I ESD performance:

Note 1: To ensure the high-impedance state during power up or power

down, OE should be tied to V

value of the resistor is determined by the current-sourcing capability of the

driver.

Pin Descriptions

Pin Names

3.5 ns max for 3.0V to 3.6V V

3.9 ns max for 2.3V to 2.7V V

6.8 ns max for 1.65V to 1.95V V

Human body model > 2000V

Machine model > 200V

–D

–O

Package Description

to O

)

supply operation

Output Enable Input (Active LOW)

through a pull-up resistor; the minimum

Latch Enable Input

November 2001

Revised November 2001

Description

Outputs

Inputs

www.fairchildsemi.com

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74ALVC16841MTD Summary of contents

Page 1

... CMOS power dissipation. Ordering Code: Order Number Package Number 74ALVC16841MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol © ...

Page 2

Connection Diagram Functional Description The 74ALVC16841 contains twenty D-type latches with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 20-bit operation. The ...

Page 3

Absolute Maximum Ratings Supply Voltage ( Input Voltage ( − 0. Output Voltage (V ) (Note Input Diode Current ( < Output Diode Current ...

Page 4

AC Electrical Characteristics Symbol Parameter = 3.3V ± 0. Min Propagation Delay PHL PLH 1.3 Bus to Bus Propagation Delay PHL PLH 1 Bus Output Enable Time ...

Page 5

AC Loading and Waveforms FIGURE 1. AC Test Circuit (Input Characteristics 1MHz; t Symbol 3.3V ± 0. − 0. ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...

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