74ALVC162373T Fairchild Semiconductor, 74ALVC162373T Datasheet
74ALVC162373T
Manufacturer Part Number
74ALVC162373T
Description
IC LATCH TRANSP 16BIT 48TSSOP
Manufacturer
Fairchild Semiconductor
Series
74ALVCr
Datasheet
1.74ALVC162373T.pdf
(6 pages)
Specifications of 74ALVC162373T
Logic Type
D-Type Transparent Latch
Circuit
8:8
Output Type
Tri-State
Voltage - Supply
1.65 V ~ 3.6 V
Independent Circuits
2
Delay Time - Propagation
1ns
Current - Output High, Low
12mA, 12mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74ALVC162373TX
Manufacturer:
FAIRCHILD/仙童
Quantity:
20 000
© 2001 Fairchild Semiconductor Corporation
Ordering Number Package Number
74ALVC162373T
74ALVC162373
Low Voltage 16-Bit Transparent Latch
with 3.6V Tolerant Inputs and Outputs
and 26 Series Resistors in Outputs
General Description
The ALVC162373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear to be transparent to the data when the Latch enable
(LE) is HIGH. When LE is LOW, the data that meets the
setup time is latched. Data appears on the bus when the
Output Enable (OE) is LOW. When OE is HIGH, the out-
puts are in a high impedance state.
The ALVC162373 is also designed with 26
the outputs. This design reduces line noise in applications
such as memory address drivers, clock drivers and bus
transceivers/transmitters.
The 74ALVC162373 is designed for low voltage (1.65V to
3.6V) V
The 74ALVC162373 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
CC
applications with I/O compatibility up to 3.6V.
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
DS500709
resistors in
Features
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to V
value of the resistor is determined by the current-sourcing capability of the
driver.
Pin Descriptions
1.65V to 3.6V V
3.6V tolerant inputs and outputs
26 series resistors in outputs
t
Power-off high impedance inputs and outputs
Support live insertion and withdrawal (Note 1)
Uses patented noise/EMI reduction circuitry
Latchup conforms to JEDEC JED78
ESD performance:
PD
Pin Names
3.8 ns max for 3.0V to 3.6V V
5.0 ns max for 2.3V to 2.7V V
9.0 ns max for 1.65V to 1.95V V
Human body model
Machine model
O
(I
I
OE
0
0
LE
Package Description
n
–I
–O
to O
15
n
n
15
n
)
CC
supply operation
Output Enable Input (Active LOW)
200V
CC
2000V
through a pull-up resistor; the minimum
Latch Enable Input
November 2001
Revised November 2001
Description
CC
CC
Outputs
Inputs
CC
www.fairchildsemi.com
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Datasheet:
74ALVC162373T Summary of contents
Page 1
... CMOS power dissipation. Ordering Code: Ordering Number Package Number 74ALVC162373T MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. ...
Page 2
Connection Diagram Functional Description The 74ALVC162373 contains sixteen edge D-type latches with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. ...
Page 3
Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage (V ) (Note 3) 0. Input Diode Current ( Output Diode Current (I ) ...
Page 4
AC Electrical Characteristics Symbol Parameter V CC Min Propagation Delay PHL PLH 1.3 Bus to Bus Propagation Delay PHL PLH 1 Bus Output Enable Time 1.3 PZL PZH t ...
Page 5
AC Loading and Waveforms FIGURE 1. AC Test Circuit (Input Characteristics: f Symbol 3.3V 0. FIGURE 2. Waveform for Inverting and ...
Page 6
Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...