74ACT373TTR STMicroelectronics, 74ACT373TTR Datasheet

IC LATCH OCTAL D 3ST 20-TSSOP

74ACT373TTR

Manufacturer Part Number
74ACT373TTR
Description
IC LATCH OCTAL D 3ST 20-TSSOP
Manufacturer
STMicroelectronics
Series
74ACTr
Datasheet

Specifications of 74ACT373TTR

Logic Type
D-Type Transparent Latch
Circuit
8:8
Output Type
Tri-State
Voltage - Supply
4.5 V ~ 5.5 V
Independent Circuits
1
Delay Time - Propagation
6ns
Current - Output High, Low
24mA, 24mA
Operating Temperature
-55°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-7720-2
74ACT373TTR
DESCRIPTION
The 74ACT373 is a high-speed CMOS OCTAL
D-TYPE LATCH with 3 STATE OUTPUT NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C
technology.
These 8 bit D-Type latch are controlled by a latch
enable input (LE) and an output enable input (OE).
When the (LE) input is high , the Q outputs follow
the data (D) inputs . When the (LE) is taken low,
the Q outputs will be latched at the logic levels set
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 2001
HIGH SPEED: t
LOW POWER DISSIPATION:
I
COMPATIBLE WITH TTL OUTPUTS
V
50 TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
BALANCED PROPAGATION DELAYS:
t
OPERATING VOLTAGE RANGE:
V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 373
IMPROVED LATCH-UP IMMUNITY
CC
PLH
OH
IH
CC
= 4 A(MAX.) at T
= 2V (MIN.), V
| = I
(OPR) = 4.5V to 5.5V
t
PHL
OL
= 24mA (MIN)
PD
IL
= 6ns (TYP.) at V
= 0.8V (MAX.)
A
=25°C
WITH 3 STATE OUTPUTS (NON INVERTED)
CC
= 5V
2
MOS
ORDER CODES
up at the D inputs. When the (OE) input is low, the
8 outputs will be in a normal logic state (high or
low logic level); when the (OE) input is high, the
outputs will be in a high impedance state.
This device is designed to interface directly High
Speed CMOS systems with TTL and NMOS
components.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PACKAGE
TSSOP
SOP
DIP
DIP
OCTAL D-TYPE LATCH
74ACT373M
74ACT373B
TUBE
SOP
74ACT373
74ACT373MTR
74ACT373TTR
TSSOP
T & R
1/11

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74ACT373TTR Summary of contents

Page 1

... This device is designed to interface directly High 2 Speed CMOS systems with TTL and NMOS MOS components. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. 74ACT373 SOP TSSOP T & R 74ACT373MTR 74ACT373TTR 1/11 ...

Page 2

INPUT AND OUTPUT EQUIVALENT CIRCUIT TRUTH TABLE INPUTS Don’t care Z : High Impedance NOTE: Outputs are latched at the time when the input is taken LOW logic level LOGIC DIAGRAM ...

Page 3

ABSOLUTE MAXIMUM RATINGS Symbol Parameter V Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Current ...

Page 4

DC SPECIFICATIONS Test Condition Symbol Parameter V CC (V) V High Level Input 4 Voltage 5.5 V Low Level Input 4 Voltage 5.5 V High Level Output 4.5 OH Voltage 5.5 4.5 5.5 V Low ...

Page 5

CAPACITIVE CHARACTERISTICS Test Condition Symbol Parameter V CC (V) C Input Capacitance 5.0 IN Output C 5.0 OUT Capacitance C Power Dissipation PD Capacitance (note 5 defined as the value of the IC’s internal equivalent capacitance ...

Page 6

WAVEFORM 1: PROPAGATION DELAYS, LE MINIMUN PULSE WIDTH SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle) 6/11 ...

Page 7

WAVEFORM 3: PROPAGATION DELAYS TIME (f=1MHz; 50% duty cycle) 74ACT373 7/11 ...

Page 8

Plastic DIP-20 (0.25) MECHANICAL DATA mm DIM. MIN. TYP. a1 0.254 B 1.39 b 0. 8.5 e 2.54 e3 22. 3.3 Z 8/11 inch MAX. MIN. TYP. 0.010 1.65 0.055 0.018 0.010 ...

Page 9

SO-20 MECHANICAL DATA mm DIM. MIN. TYP 0. 0.35 b1 0. 12.60 E 10.00 e 1.27 e3 11.43 F 7. inch MAX. MIN. TYP. 2.65 0.20 0.004 2.45 ...

Page 10

TSSOP20 MECHANICAL DATA mm DIM. MIN. TYP 0.05 0.10 A2 0.85 0.9 b 0.19 c 0.09 D 6.4 6.5 E 6.25 6.4 E1 4.3 4.4 e 0.65 BSC 0.50 0. ...

Page 11

... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied ...

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